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| m68hc08 microcontrollers freescale.com MC68HC708MP16 data sheet rev. 3.1 MC68HC708MP16/d july 28, 2005
MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor list of sections 3 non-disclosure agreement required technical data ? MC68HC708MP16 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . 29 section 2. memory map . . . . . . . . . . . . . . . . . . . . . . . . . 39 section 3. random-access memory (ram) . . . . . . . . . 53 section 4. eprom/otprom . . . . . . . . . . . . . . . . . . . . . . 55 section 5. configuration regist er (config). . . . . . . . . 59 section 6. central processor unit (cpu) . . . . . . . . . . . . 63 section 7. system integration module (sim) . . . . . . . . . 81 section 8. clock generator module (cgm) . . . . . . . . 103 section 9. pulse width modulator for motor control (pwmmc) . . . . . . . . . . . . . . . . . . . . . . . . . 129 section 10. monitor rom (mon) . . . . . . . . . . . . . . . . . 191 section 11. timer interface module a (tima) . . . . . . . 201 section 12. timer interface module b (timb) . . . . . . . 225 section 13. serial peripheral interface module (spi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 section 14. serial communications interface module (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 section 15. input/output (i/o) port s . . . . . . . . . . . . . . 317 section 16. computer operating properly (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 section 17. external interrupt (irq ) . . . . . . . . . . . . . . . 339 non-disclosure agreement required list of sections technical data MC68HC708MP16 ? rev. 3.1 4 list of sections freescale semiconductor section 18. low-voltage inhibit (l vi). . . . . . . . . . . . . . 347 section 19. analog-to-digital converter (adc) . . . . . 353 section 20. power-on reset (por) . . . . . . . . . . . . . . . 365 section 21. electrical specificati ons . . . . . . . . . . . . . . 367 section 22. mechanical specifications . . . . . . . . . . . . 379 section 23. ordering information. . . . . . . . . . . . . . . . . 381 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor table of contents 5 non-disclosure agreement required technical data ? MC68HC708MP16 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.5.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . 35 1.5.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . 35 1.5.3 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.5.4 external interrupt pin (irq1 /v pp ) . . . . . . . . . . . . . . . . . . . 36 1.5.5 cgm power supply pins (v dda and v ssa ). . . . . . . . . . . . 36 1.5.6 external filter capacitor pin (c gmxfc). . . . . . . . . . . . . . 36 1.5.7 analog power supply pins (v ddad /v ddaref and v ssad ) . . . . . . . . . . . . . . . . . . . . 36 1.5.8 adc voltage decoup ling capacitor pin (v adcap ) . . . . . . 36 1.5.9 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . 37 1.5.10 port a input/output (i/o) pins (pta7?pta0) . . . . . . . . . . 37 1.5.11 port b i/o pins (ptb7/atd7?ptb 0/atd0). . . . . . . . . . . . 37 1.5.12 port c i/o pins (ptc6?ptc2 and ptc1/atd9?ptc0/atd8) . . . . . . . . . . . . . . . . . . 37 1.5.13 port d input-only pins (ptd6/is3 ?ptd4/is1 and ptd3/fault4?ptd0/fault1) . . . . . . . . . . . . . . 37 1.5.14 pwm pins (pwm6?pwm1). . . . . . . . . . . . . . . . . . . . . . . . 38 1.5.15 pwm ground pin (pwmgn d) . . . . . . . . . . . . . . . . . . . . . 38 1.5.16 port e i/o pins (pte7/tch3b?pte3/tclkb and pte2/tch1a?pte0/tclka) . . . . . . . . . . . . . . . . 38 1.5.17 port f i/o pins (ptf5/txd?ptf4/rxd and ptf3/miso?ptf0/ spsck) . . . . . . . . . . . . . . . . . 38 non-disclosure agreement required table of contents technical data MC68HC708MP16 ? rev. 3.1 6 table of contents freescale semiconductor section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.4 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 section 4. eprom/otprom 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.4 eprom/otprom control r egister. . . . . . . . . . . . . . . . . . . . 56 4.5 eprom/otprom progra mming sequence . . . . . . . . . . . . . 57 section 5. configurat ion register (config) 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 section 6. central pr ocessor unit (cpu) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table of contents MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor table of contents 7 non-disclosure agreement required 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.4.1 accumulator (a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.4.2 index register (h:x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.4.3 stack pointer (sp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.4.4 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.4.5 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . 69 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 section 7. system integration module (sim) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 85 7.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.3.2 clock start-up from por or lvi reset . . . . . . . . . . . . . . . . 85 7.3.3 clocks in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.4 reset and system initializa tion. . . . . . . . . . . . . . . . . . . . . . . . . 86 7.4.1 external pin reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.4.2 active resets from inte rnal sources . . . . . . . . . . . . . . . . . . 88 7.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 7.4.2.2 computer operati ng properly (cop) reset. . . . . . . . . . . 90 7.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 7.4.2.5 low-voltage inhibit (l vi) reset . . . . . . . . . . . . . . . . . . . . 91 7.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . . 91 7.5.2 sim counter and reset st ates . . . . . . . . . . . . . . . . . . . . . . 91 7.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.6.3 status flag protection in break mode. . . . . . . . . . . . . . . . . 96 non-disclosure agreement required table of contents technical data MC68HC708MP16 ? rev. 3.1 8 table of contents freescale semiconductor 7.7 low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.7.2 sim break status regist er . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.7.3 sim reset status regi ster . . . . . . . . . . . . . . . . . . . . . . . . 101 7.7.4 sim break flag control register . . . . . . . . . . . . . . . . . . . 102 section 8. clock generator module (cgm) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 8.4.1 crystal oscillator circ uit . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.4.2 phase-locked loop circ uit (pll) . . . . . . . . . . . . . . . . . . . 107 8.4.2.1 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.4.2.2 acquisition and tracking modes . . . . . . . . . . . . . . . . . . 109 8.4.2.3 manual and automatic pll b andwidth modes . . . . . . . 109 8.4.2.4 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.4.2.5 special programming exceptions . . . . . . . . . . . . . . . . . 112 8.4.3 base clock selector circuit. . . . . . . . . . . . . . . . . . . . . . . . 112 8.4.4 cgm external connectio ns. . . . . . . . . . . . . . . . . . . . . . . . 113 8.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.5.1 crystal amplifier input pin (osc1) . . . . . . . . . . . . . . . . . . 114 8.5.2 crystal amplifier ou tput pin (osc2) . . . . . . . . . . . . . . . . . 114 8.5.3 external filter capacitor pin (c gmxfc). . . . . . . . . . . . . . 114 8.5.4 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . 115 8.5.5 oscillator enable signal (simoscen) . . . . . . . . . . . . . . . 115 8.5.6 crystal output frequency signal (cgmxclk) . . . . . . . . . 115 8.5.7 cgm base clock output (cgmout) . . . . . . . . . . . . . . . . 115 8.5.8 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . 116 8.6 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.6.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.6.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . 119 8.6.3 pll programming regist er . . . . . . . . . . . . . . . . . . . . . . . . 121 8.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 8.8 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table of contents MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor table of contents 9 non-disclosure agreement required 8.9 cgm during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.10 acquisition/lock time spec ifications . . . . . . . . . . . . . . . . . . . 124 8.10.1 acquisition/lock time definitions . . . . . . . . . . . . . . . . . . . 124 8.10.2 parametric influences on reaction time . . . . . . . . . . . . . 126 8.10.3 choosing a filter capac itor. . . . . . . . . . . . . . . . . . . . . . . . 127 8.10.4 reaction time calculat ion . . . . . . . . . . . . . . . . . . . . . . . . 127 section 9. pulse width modulator for motor control (pwmmc) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.4 timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.4.1 resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.4.2 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.5 pwm generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.5.1 load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.5.2 pwm data overflow and underf low conditions . . . . . . . . 142 9.6 output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.6.1 selecting six independent pwms or three complementary pwm pair s . . . . . . . . . . . . . 142 9.6.2 dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 9.6.3 top/bottom correction . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9.6.3.1 manual correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.6.3.2 automatic correction . . . . . . . . . . . . . . . . . . . . . . . . . . .154 9.6.4 output polarity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 9.6.5 output port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 9.7 fault protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 9.7.1 fault condition input pi ns . . . . . . . . . . . . . . . . . . . . . . . . . 164 9.7.1.1 fault pin filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 9.7.1.2 automatic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 9.7.1.3 manual mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 9.7.2 software output disabl e . . . . . . . . . . . . . . . . . . . . . . . . . . 168 9.7.3 output port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 non-disclosure agreement required table of contents technical data MC68HC708MP16 ? rev. 3.1 10 table of contents freescale semiconductor 9.8 initialization and the pwm en bit . . . . . . . . . . . . . . . . . . . . . . 169 9.9 pwm operation in wait mode . . . . . . . . . . . . . . . . . . . . . . . . 171 9.10 pwm operation in break mode . . . . . . . . . . . . . . . . . . . . . . .171 9.11 control logic block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 9.11.1 pwm counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . 172 9.11.2 pwm counter modulo registers. . . . . . . . . . . . . . . . . . . .173 9.11.3 pwm x value registers . . . . . . . . . . . . . . . . . . . . . . . . . . 174 9.11.4 pwm control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 175 9.11.5 pwm control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 177 9.11.6 dead-time write-once register . . . . . . . . . . . . . . . . . . . .179 9.11.7 pwm disable mapping write-once register . . . . . . . . . . 180 9.11.8 fault control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 9.11.9 fault status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 9.11.10 fault acknowledge regist er . . . . . . . . . . . . . . . . . . . . . . .185 9.11.11 pwm output control r egister. . . . . . . . . . . . . . . . . . . . . . 186 9.12 pwm glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 section 10. monitor rom (mon) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 10.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 10.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 10.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table of contents MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor table of contents 11 non-disclosure agreement required section 11. timer inte rface module a (tima) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 11.4.1 tima counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . 205 11.4.2 input capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 11.4.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 11.4.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 206 11.4.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .207 11.4.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . 207 11.4.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 209 11.4.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 210 11.4.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 11.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 11.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 11.7 tima during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . . 213 11.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 11.8.1 tima clock pin (pte0/ tclka). . . . . . . . . . . . . . . . . . . . . 213 11.8.2 tima channel i/o pins (pte1/tch0a:pte2/tch1a) . . . . . . . . . . . . . . . . . . . 214 11.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 11.9.1 tima status and cont rol register. . . . . . . . . . . . . . . . . . . 215 11.9.2 tima counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . 217 11.9.3 tima counter modulo registers . . . . . . . . . . . . . . . . . . . .218 11.9.4 tima channel status and control registers . . . . . . . . . . 219 11.9.5 tima channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . 223 section 12. timer inte rface module b (timb) 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 non-disclosure agreement required table of contents technical data MC68HC708MP16 ? rev. 3.1 12 table of contents freescale semiconductor 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 12.4.1 timb counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . 230 12.4.2 input capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 12.4.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 12.4.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 230 12.4.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .231 12.4.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . 232 12.4.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 233 12.4.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 234 12.4.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 12.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 12.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 12.7 timb during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . . 238 12.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 12.8.1 timb clock pin (pte3/ tclkb). . . . . . . . . . . . . . . . . . . . . 238 12.8.2 timb channel i/o pins (pte4/tch0b:pte7/tch3b) . . . . . . . . . . . . . . . . . . . 239 12.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 12.9.1 timb status and cont rol register. . . . . . . . . . . . . . . . . . . 240 12.9.2 timb counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . 242 12.9.3 timb counter modulo registers . . . . . . . . . . . . . . . . . . . .243 12.9.4 timb channel status and control registers . . . . . . . . . . 244 12.9.5 timb channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . 248 section 13. serial peripher al interface module (spi) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 13.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 13.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 13.5.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 13.5.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 table of contents MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor table of contents 13 non-disclosure agreement required 13.6 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 13.6.1 clock phase and polarity controls . . . . . . . . . . . . . . . . . . 258 13.6.2 transmission format wh en cpha = 0 . . . . . . . . . . . . . . . 258 13.6.3 transmission format when cpha = 1 . . . . . . . . . . . . . . . 260 13.6.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . 261 13.7 queuing transmissi on data . . . . . . . . . . . . . . . . . . . . . . . . . . 263 13.8 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 13.8.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 13.8.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 13.9 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 13.10 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 13.11 low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 13.12 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 272 13.13 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 13.13.1 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . .273 13.13.2 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . .274 13.13.3 spsck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 13.13.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 13.13.5 cgnd (clock ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 13.14 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 13.14.1 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 13.14.2 spi status and control register . . . . . . . . . . . . . . . . . . . .279 13.14.3 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 section 14. serial communications interface module (sci) 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 non-disclosure agreement required table of contents technical data MC68HC708MP16 ? rev. 3.1 14 table of contents freescale semiconductor 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 14.4.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14.4.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14.4.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14.4.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 289 14.4.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 14.4.2.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 14.4.2.5 inversion of transm itted output. . . . . . . . . . . . . . . . . . . 292 14.4.2.6 transmitter in terrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .292 14.4.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 14.4.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 14.4.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 14.4.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 14.4.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 14.4.3.5 receiver wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 14.4.3.6 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 14.4.3.7 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 14.5 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 14.6 sci during break module interrupts. . . . . . . . . . . . . . . . . . . .299 14.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 14.7.1 ptf5/txd (transmit data ) . . . . . . . . . . . . . . . . . . . . . . . . 300 14.7.2 ptf4/rxd (receive data ). . . . . . . . . . . . . . . . . . . . . . . . . 300 14.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 14.8.1 sci control regi ster 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .301 14.8.2 sci control regi ster 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .304 14.8.3 sci control regi ster 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .307 14.8.4 sci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 14.8.5 sci status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 14.8.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314 14.8.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . 314 section 15. input/output (i/o) ports 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 table of contents MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor table of contents 15 non-disclosure agreement required 15.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 15.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 15.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 320 15.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 15.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 15.4.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . 322 15.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 15.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 15.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . 325 15.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 15.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 15.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 15.7.2 data direction register e . . . . . . . . . . . . . . . . . . . . . . . . . 329 15.8 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 15.8.1 port f data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 15.8.2 data direction register f . . . . . . . . . . . . . . . . . . . . . . . . . 331 section 16. computer op erating properly (cop) 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 16.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.4.1 cgmxclk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.4.2 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.4.3 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.4.4 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 16.4.5 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 16.4.6 copd (cop disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 16.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 16.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 16.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 16.8 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 16.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 337 non-disclosure agreement required table of contents technical data MC68HC708MP16 ? rev. 3.1 16 table of contents freescale semiconductor section 17. external interrupt (irq) 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 17.5 irq1 /v pp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343 17.6 irq module during break mode. . . . . . . . . . . . . . . . . . . . . . . 344 17.7 irq status and control register . . . . . . . . . . . . . . . . . . . . . . 345 section 18. low-volt age inhibit (lvi) 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348 18.4.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 18.4.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . 349 18.4.3 false reset protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 18.5 lvi status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 18.6 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351 18.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 section 19. analog-to-dig ital converter (adc) 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 19.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 19.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 19.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 table of contents MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor table of contents 17 non-disclosure agreement required 19.4.4 continous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 19.4.5 accuracy and precision. . . . . . . . . . . . . . . . . . . . . . . . . . .357 19.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 19.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 19.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 19.7.1 adc analog power pin (v ddad ) . . . . . . . . . . . . . . . . . . . .358 19.7.2 adc analog ground pin (v ssad ) . . . . . . . . . . . . . . . . . . . 358 19.7.3 adc voltage reference pin (v ddaref ) . . . . . . . . . . . . . . 358 19.7.4 adc voltage decoup ling capacitor pin (v adcap ) . . . . . . 358 19.7.5 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . 359 19.7.6 adc voltage in ( advin) . . . . . . . . . . . . . . . . . . . . . . . . . . 359 19.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 19.8.1 adc status and control register . . . . . . . . . . . . . . . . . . . 360 19.8.2 adc data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363 19.8.3 adc clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 section 20. power-on reset (por) 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 20.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365 section 21. electrical specifications 21.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 21.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 368 21.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 369 21.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 21.6 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 370 21.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 21.8 serial peripheral interface characteri stics . . . . . . . . . . . . . . . 372 21.9 timer interface module characterist ics . . . . . . . . . . . . . . . . . 375 non-disclosure agreement required table of contents technical data MC68HC708MP16 ? rev. 3.1 18 table of contents freescale semiconductor 21.10 clock generation modu le electrical characteri stics. . . . . . . . 375 21.11 analog-to-digital converter (adc) characteristics. . . . . . . . . 377 21.12 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 section 22. mechanic al specifications 22.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 22.3 plastic quad flat pack (qfp). . . . . . . . . . . . . . . . . . . . . . . . . 380 section 23. ordering information 23.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 23.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 glossary MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor list of figures 19 non-disclosure agreement required technical data ? MC68HC708MP16 list of figures figure title page 1-1 mcu block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1-2 sdip pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1-3 qfp pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1-4 power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2-1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2-2 control, status, and da ta registers . . . . . . . . . . . . . . . . . . 42 4-1 eprom/otprom control register (epmcr) . . . . . . . . . 56 5-1 configuration register (config) . . . . . . . . . . . . . . . . . . . . 60 6-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6-3 index register (h:x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . 69 7-1 sim block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7-2 sim i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . 84 7-3 cgm clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 7-4 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7-5 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7-6 sources of internal re set. . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7-7 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 7-8 interrupt entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7-9 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7-10 interrupt recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7-11 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . . 95 non-disclosure agreement required list of figures technical data MC68HC708MP16 ? rev. 3.1 20 list of figures freescale semiconductor figure title page 7-12 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 7-13 wait recovery from interrupt or break. . . . . . . . . . . . . . . . . 98 7-14 wait recovery from internal rese t . . . . . . . . . . . . . . . . . . . 98 7-15 sim break status regi ster (sbsr) . . . . . . . . . . . . . . . . . . . 99 7-16 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . 101 7-17 sim break flag control register (sbfcr) . . . . . . . . . . . . 102 8-1 cgm block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8-2 cgm i/o regist er summary . . . . . . . . . . . . . . . . . . . . . . .107 8-3 cgm external connectio ns . . . . . . . . . . . . . . . . . . . . . . . . 114 8-4 cgm i/o regist er summary . . . . . . . . . . . . . . . . . . . . . . .116 8-5 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . 117 8-6 pll bandwidth control register (pbwc) . . . . . . . . . . . . . 119 8-7 pll programming regi ster (ppg) . . . . . . . . . . . . . . . . . . . 121 9-1 pwm module block diagr am . . . . . . . . . . . . . . . . . . . . . . . 131 9-2 pwmmc register summ ary . . . . . . . . . . . . . . . . . . . . . . .132 9-3 center-aligned pw m (positive polarity). . . . . . . . . . . . . . . 135 9-4 edge-aligned pwm (positive polari ty) . . . . . . . . . . . . . . . . 136 9-5 reload frequency change . . . . . . . . . . . . . . . . . . . . . . . . 138 9-6 pwm interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9-7 center-aligned pwm va lue loading . . . . . . . . . . . . . . . . . 140 9-8 center-aligned loading of modulus . . . . . . . . . . . . . . . . . . 140 9-9 edge-aligned pwm valu e loading . . . . . . . . . . . . . . . . . . 141 9-10 edge-aligned modulus loading . . . . . . . . . . . . . . . . . . . . . 141 9-11 complementary pairing . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9-12 typical ac motor drive . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9-13 dead-time generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 9-14 effects of dead-time insertion. . . . . . . . . . . . . . . . . . . . . . 147 9-15 dead-time at duty cycle boundarie s . . . . . . . . . . . . . . . . 147 9-16 dead-time and small pulse widths. . . . . . . . . . . . . . . . . . 148 9-17 current convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 9-18 deadtime distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 9-19 sinusoidal distortion of load voltage . . . . . . . . . . . . . . . . 150 9-20 internal correcti on logic when isens[1:0] = 0x . . . . . . . . 152 9-21 output voltage waveform s . . . . . . . . . . . . . . . . . . . . . . . . 153 list of figures MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor list of figures 21 non-disclosure agreement required figure title page 9-22 dtx bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 9-23 internal correcti on logic when isens[1:0] = 10 . . . . . . . . 155 9-24 internal correcti on logic when isens[1:0] = 11 . . . . . . . . 155 9-25 correction with positi ve current. . . . . . . . . . . . . . . . . . . . . 156 9-26 correction with negative current . . . . . . . . . . . . . . . . . . . .156 9-27 pwm polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 9-28 pwm output contro l register (pwmout) . . . . . . . . . . . . 158 9-29 dead-time insertion during outc tl = 1 . . . . . . . . . . . . . 160 9-30 dead-time insertion during outc tl = 1 . . . . . . . . . . . . . 160 9-31 pwm disabling scheme. . . . . . . . . . . . . . . . . . . . . . . . . . .161 9-32 pwm disabling scheme. . . . . . . . . . . . . . . . . . . . . . . . . . .162 9-33 pwm disable mapping write-once register (dismap). . . . . . . . . . . . . . . . . . . 163 9-34 pwm disabling decode scheme . . . . . . . . . . . . . . . . . . . .164 9-35 pwm disabling in automatic mode . . . . . . . . . . . . . . . . . . 165 9-36 pwm disabling in manual mode (example 1) . . . . . . . . . . 167 9-37 pwm disabling in manual mode (example 2) . . . . . . . . . . 167 9-38 pwm software disable . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 9-39 pwmen and pwm pins. . . . . . . . . . . . . . . . . . . . . . . . . . .170 9-40 pwm counter registers (pcnth :pcntl) . . . . . . . . . . . . 172 9-41 pwm counter modulo regi sters (pdmodh:pmodl). . . . 173 9-42 pwm x value registers (pvalx h:pvalxl). . . . . . . . . . . 174 9-43 pwm control register 1 (pctl1) . . . . . . . . . . . . . . . . . . . 175 9-44 pwm control register 2 (pctl2) . . . . . . . . . . . . . . . . . . . 177 9-45 dead-time write-once register (deadtm) . . . . . . . . . . . 179 9-46 pwm disable mapping write-once register (dismap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 9-47 fault control register (fcr) . . . . . . . . . . . . . . . . . . . . . . .180 9-48 fault status register (fsr) . . . . . . . . . . . . . . . . . . . . . . . . 183 9-49 fault acknowledge regi ster (ftack) . . . . . . . . . . . . . . . . 185 9-50 pwm output contro l register (pwmout) . . . . . . . . . . . . 186 9-51 pwm clock cycle and pwm cycle definitions . . . . . . . . . 188 9-52 pwm load cycle/frequ ency definition . . . . . . . . . . . . . . . 189 10-1 monitor mode circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 10-2 monitor data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 non-disclosure agreement required list of figures technical data MC68HC708MP16 ? rev. 3.1 22 list of figures freescale semiconductor figure title page 10-3 sample monitor waveforms . . . . . . . . . . . . . . . . . . . . . . . . 195 10-4 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 10-5 break transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 11-1 tima block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 11-2 tima i/o register su mmary . . . . . . . . . . . . . . . . . . . . . . . 204 11-3 pwm period and pulse width . . . . . . . . . . . . . . . . . . . . . . 208 11-4 tima status and c ontrol register (tasc). . . . . . . . . . . . . 215 11-5 tima counter registers (tac nth:tacntl) . . . . . . . . . . 217 11-6 tima counter modulo registers (tamodh:tamodl) . . . . . . . . . . . . . . . . . . . . . . . . . . 218 11-7 tima channel status and control registers (tasc0:tasc1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 11-8 chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 11-9 tima channel registers (ta ch0h/l:tach1h/l) . . . . . . . 223 12-1 timb block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 12-2 timb i/o register su mmary . . . . . . . . . . . . . . . . . . . . . . .228 12-3 pwm period and pulse width . . . . . . . . . . . . . . . . . . . . . . 233 12-4 timb status and c ontrol register (tbsc). . . . . . . . . . . . . 240 12-5 timb counter registers (tbc nth:tbcntl) . . . . . . . . . . 242 12-6 timb counter modulo registers (tbmodh:tbmodl) . . . . . . . . . . . . . . . . . . . . . . . . . . 243 12-7 timb channel status and control registers (tbsc0:tbsc3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 12-8 chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 12-9 timb channel registers (tb ch0h/l:tbch3h/l) . . . . . . 248 13-1 spi module block diagram . . . . . . . . . . . . . . . . . . . . . . . . 254 13-2 spi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . 255 13-3 full-duplex master-slave connecti ons . . . . . . . . . . . . . . . 256 13-4 transmission format (cpha = 0) . . . . . . . . . . . . . . . . . . . 259 13-5 cpha/ss timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 13-6 transmission format (cpha = 1) . . . . . . . . . . . . . . . . . . . 260 13-7 transmission start delay (master). . . . . . . . . . . . . . . . . . . 262 13-8 sprf/spte cpu interrupt timing. . . . . . . . . . . . . . . . . . . 263 list of figures MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor list of figures 23 non-disclosure agreement required figure title page 13-9 missed read of overflow condition . . . . . . . . . . . . . . . . . . 265 13-10 clearing sprf w hen ovrf interrupt is not enabled . . . . 266 13-11 spi interrupt request generation . . . . . . . . . . . . . . . . . . . 270 13-12 cpha/ss timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 13-13 spi control register (spcr) . . . . . . . . . . . . . . . . . . . . . . . 277 13-14 spi status and control register (spscr). . . . . . . . . . . . . 279 13-15 spi data register ( spdr) . . . . . . . . . . . . . . . . . . . . . . . . . 282 14-1 sci module block diagr am . . . . . . . . . . . . . . . . . . . . . . . . 286 14-2 sci i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . 287 14-3 sci data formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14-4 sci transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 14-5 sci receiver block diagram . . . . . . . . . . . . . . . . . . . . . . .293 14-6 receiver data sampling. . . . . . . . . . . . . . . . . . . . . . . . . . .295 14-7 sci control regi ster 1 (scc1) . . . . . . . . . . . . . . . . . . . . . 301 14-8 sci control regi ster 2 (scc2) . . . . . . . . . . . . . . . . . . . . . 304 14-9 sci control regi ster 3 (scc3) . . . . . . . . . . . . . . . . . . . . . 307 14-10 sci status register 1 (scs1) . . . . . . . . . . . . . . . . . . . . . . 309 14-11 flag clearing sequence. . . . . . . . . . . . . . . . . . . . . . . . . . .312 14-12 sci status register 2 (scs2) . . . . . . . . . . . . . . . . . . . . . . 313 14-13 sci data register ( scdr). . . . . . . . . . . . . . . . . . . . . . . . . 314 14-14 sci baud rate regist er (scbr) . . . . . . . . . . . . . . . . . . . . 314 15-1 i/o port register summary . . . . . . . . . . . . . . . . . . . . . . .318 15-2 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . 320 15-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . 320 15-4 port a i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 15-5 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . 322 15-6 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . 322 15-7 port b i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 15-8 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . . 324 15-9 data direction register c (ddrc). . . . . . . . . . . . . . . . . . . 325 15-10 port c i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 15-11 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . 326 15-12 port d input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 15-13 port e data register (pte) . . . . . . . . . . . . . . . . . . . . . . . . 328 non-disclosure agreement required list of figures technical data MC68HC708MP16 ? rev. 3.1 24 list of figures freescale semiconductor figure title page 15-14 data direction regist er e (ddre) . . . . . . . . . . . . . . . . . . . 329 15-15 port e i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 15-16 port f data register (ptf) . . . . . . . . . . . . . . . . . . . . . . . . 330 15-17 data direct register f (ddrf) . . . . . . . . . . . . . . . . . . . . . 331 15-18 port f i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 16-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 16-2 cop i/o register summ ary . . . . . . . . . . . . . . . . . . . . . . . . 334 16-3 cop control register (copctl). . . . . . . . . . . . . . . . . . . .336 17-1 irq module block diagram . . . . . . . . . . . . . . . . . . . . . . . . 340 17-2 irq i/o register summ ary . . . . . . . . . . . . . . . . . . . . . . . . 340 17-3 irq interrupt flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 17-4 irq status and control register (iscr) . . . . . . . . . . . . . . 345 18-1 lvi module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 348 18-2 lvi i/o register summ ary . . . . . . . . . . . . . . . . . . . . . . . . . 349 18-3 lvi status register (l visr). . . . . . . . . . . . . . . . . . . . . . . . 350 19-1 adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 19-2 adc status and cont rol register (adscr). . . . . . . . . . . . 360 19-3 adc data register ( adr) . . . . . . . . . . . . . . . . . . . . . . . . . 363 19-4 adc clock register (adclkr) . . . . . . . . . . . . . . . . . . . . . 363 20-1 por block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 21-1 spi master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 21-2 spi slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 22-1 MC68HC708MP16fu (c ase #840b-01) . . . . . . . . . . . . . . 380 MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor list of tables 25 non-disclosure agreement required technical data ? MC68HC708MP16 list of tables table title page 2-1 vector addresses ....... ................ ................. .............. .......... 51 6-1 instruction set summary . .............. .............. .............. .......... 72 6-2 opcode map................ ................ ................. .............. .......... 80 7-1 signal name convention s .................. .............. ........... ........ 84 7-2 pin bit set timing ....... ................ ................. .............. .......... 87 8-1 vco frequency multiplier (n) sele ction ............. ............... 122 9-1 pwm prescaler ......... ................ ................. .............. .......... 137 9-2 pwm reload frequency ................ .............. .............. ........ 138 9-3 pwm data overflow and underf low conditions... .............. 142 9-4 correction method selection ....... ............... .............. ..........151 9-5 top/bottom manual correction ...... .............. .............. ........ 152 9-6 top/bottom current-s ense correction......... .............. ........ 154 9-7 outx bits ........ .............. .............. ............... .............. .......... 158 9-8 correction methods ....... .............. ............... .............. ..........176 9-9 pwm reload frequency ................ .............. .............. ........ 178 9-10 pwm prescaler ......... ................ ................. .............. .......... 179 9-11 outx bits ............... ................. ................ ................. .......... 187 10-1 mode selection ......... ................ ................. .............. .......... 194 10-2 mode differences ........ ................ ............... .............. .......... 195 10-3 read (read memory) command....... ........... ............ ........ 197 10-4 write (write memory) command .. .............. ............ ........ 198 10-5 iread (indexed read) command ................. ............ ........ 198 10-6 iwrite (indexed write) command. ............. .............. ........ 199 10-7 readsp (read stack pointer) command..... ............ ........ 199 non-disclosure agreement required list of tables technical data MC68HC708MP16 ? rev. 3.1 26 list of tables freescale semiconductor table title page 10-8 run (run user program) command ............. ............ ........ 200 10-9 monitor baud rate selection..... ................. .............. ..........200 11-1 prescaler selection ..... ................ ............... .............. ..........216 11-2 mode, edge, and level selection... .............. .............. ........221 12-1 prescaler selection ..... ................ ............... .............. ..........241 12-2 mode, edge, and level selection... .............. .............. ........247 13-1 pin name conventions.. .............. ............... .............. .......... 253 13-2 spi interrupts ............ ................ ................. .............. .......... 269 13-3 spi configuration ...... ................ ................. .............. .......... 276 13-4 spi master baud rate selection. ............... .............. .......... 281 14-1 start bit verification... ................ ................. .............. ..........295 14-2 data bit recovery ....... ................ ............... .............. .......... 296 14-3 stop bit recovery...... ................ ................. .............. .......... 296 14-4 character format selection ........ ............... .............. .......... 303 14-5 sci baud rate prescaling........... ............... .............. .......... 315 14-6 sci baud rate selection........... ................. .............. .......... 315 14-7 sci baud rate selection examples ............. .............. ........ 316 15-1 port a pin functions.... ................ ............... .............. .......... 321 15-2 port b pin functions.... ................ ............... .............. .......... 323 15-3 port c pin functions ................. ................. .............. .......... 326 15-4 port d pin functions ................. ................. .............. .......... 327 15-5 port e pin functions.... ................ ............... .............. .......... 330 15-6 port f pin functions.... ................ ............... .............. .......... 332 18-1 lviout bit indica tion........... ................. ................ ............. 350 19-1 mux channel select ...... .............. ............... .............. .......... 362 19-2 adc clock divide ratio .............. ............... .............. ..........364 21-1 absolute maximum ratings .............. .............. ............ ........ 368 21-2 operating range ......... ................ ............... .............. .......... 369 list of tables MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor list of tables 27 non-disclosure agreement required table title page 21-3 thermal characteristics .............. ............... .............. ..........369 21-4 dc electrical characteristics (v dd = 5.0 vdc 10%) .............. .............. .............. ........ 370 21-5 control timing (v dd = 5.0 vdc 10%).............. ................. 371 21-6 serial peripheral in terface (spi) timing (v dd = 5.0 vdc 10%) ................ .............. ............ ........ 372 21-7 tim timing ...... .............. .............. ............... .............. .......... 375 21-8 cgm component specifications .... .............. .............. ........ 375 21-9 cgm operating conditi ons .............. .............. ............ ........ 375 21-10 cgm acquisition/lock time specif ications......... ............... 376 21-11 adc characteristics .................. ................. .............. .......... 377 21-12 memory characteristics............. ................. .............. .......... 377 23-1 mc order numbers ....... .............. ............... .............. ..........383 non-disclosure agreement required list of tables technical data MC68HC708MP16 ? rev. 3.1 28 list of tables freescale semiconductor MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor general description 29 non-disclosure agreement required technical data ? MC68HC708MP16 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.5.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . . 34 1.5.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . 34 1.5.3 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.5.4 external interrupt pin (irq1 /v pp ) . . . . . . . . . . . . . . . . . . . . 35 1.5.5 cgm power supply pins (v dda and v ssa ). . . . . . . . . . . . . 35 1.5.6 external filter capacitor pin (c gmxfc). . . . . . . . . . . . . . . 35 1.5.7 analog power supply pins (v ddad /v ddaref and v ssad ) . . . . . . . . . . . . . . . . . . . . .35 1.5.8 adc voltage decoup ling capacitor pin (v adcap ) . . . . . . . 35 1.5.9 adc voltage reference low pin (vrefl) . . . . . . . . . . . . . 36 1.5.10 port a input/output (i/o) pins (pta7?pta0) . . . . . . . . . . . 36 1.5.11 port b i/o pins (ptb7/atd7?ptb 0/atd0). . . . . . . . . . . . . 36 1.5.12 port c i/o pins (ptc6?ptc2 and ptc1/atd9?ptc0/atd8) . . . . . . . . . . . . . . . . . . . 36 1.5.13 port d input-only pins (ptd6/is3 ?ptd4/is1 and ptd3/fault4?ptd0/fault1) . . . . . . . . . . . . . . . 36 1.5.14 pwm pins (pwm6?pwm1). . . . . . . . . . . . . . . . . . . . . . . . . 37 1.5.15 pwm ground pin (pwmgn d) . . . . . . . . . . . . . . . . . . . . . . 37 1.5.16 port e i/o pins (pte7/tch3b?pte3/tclkb and pte2/tch1a?pte0/tclka) . . . . . . . . . . . . . . . . . 37 1.5.17 port f i/o pins (ptf5/txd?ptf4/rxd and ptf3/miso?ptf0/ spsck) . . . . . . . . . . . . . . . . . . 37 non-disclosure agreement required general description technical data MC68HC708MP16 ? rev. 3.1 30 general description freescale semiconductor 1.2 introduction the MC68HC708MP16 is a member of the low-cost, high-performance m68hc08 family of 8-bi t microcontroller units (mcus). the m68hc08 family is based on the customer-spec ified integrated circuit (csic) design strategy. all mcus in t he family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modules, memory sizes and types, and package types. 1.3 features features of the mc 68hc708mp16 include: high-performance m68hc08 architecture fully upward-compatible objec t code with m6805, m146805, and m68hc05 families 8-mhz internal bus frequency 16 kbytes of on-chip erasabl e programmable read-only memory (eprom) or one-ti me programmable read-only memory (otprom) on-chip programming firmwa re for use with host personal computer eprom/otprom data security 1 512 bytes of on-chip ram 12-bit, 6-channel center-alig ned or edge-aligned pulse width modulator (pwmmc) 64-pin plastic quad flat pack (qfp) serial peripheral in terface module (spi) serial communications interface module (sci) 16-bit, 2-channel timer interface module (tima) 16-bit, 4-channel timer interface module (timb) 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the eprom/otprom diff icult for unauthorized users. general description MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor general description 31 non-disclosure agreement required clock generator module (cgm) digitally filtered low- voltage inhibit (lvi45) 8-bit, 10-channel analog-to-d igital convertor (adc) system protection features: ? optional computer operati ng properly (cop) reset ? low-voltage detection with optional reset ? illegal opcode detecti on with optional reset ? illegal address detecti on with optional reset ? fault detection with opt ional pwm disabling low-power design (fully static with wait mode) master reset pin and power-on reset features of the cpu08 include: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications c language support 1.4 mcu block diagram figure 1-1 shows the structure of the MC68HC708MP16. non-disclosure agreement required technical data MC68HC708MP16 ? rev. 3.1 32 general description freescale semiconductor general description figure 1-1. mcu block diagram clock generator module system integration module serial communications interface module serial peripheral interface module timer interface module a low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 96 bytes user eprom ? 16,384 bytes user ram ? 512 bytes monitor rom ? 240 bytes user eprom vector space ? 46 bytes irq module power pta ddra ddrb ptb ddrc ptc ptd ddre pte ptf ddrf internal bus osc1 osc2 cgmxfc rst irq1 /v pp v ss v dd v dda pta7?pta0 pte7/tch3b pte6/tch2b pte5/tch1b pte4/tch0b pte3/tclkb pte2/tch1a pte1/tch0a pte0/tclka ptf5/txd ptf4/rxd ptf3/miso ptf2/mosi ptf1/ss ptf0/spsck timer interface module b pulse width modulator module ptb7/atd7 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1/atd9 ptc0/atd8 ptd6/is3 ptd5/is2 ptd4/is1 ptd3/fault4 ptd2/fault3 ptd1/fault2 ptd0/fault1 pwm6?pwm1 analog-to-digital converter module v ssa v ddad /v ddaref v ssad pwmgnd v refl v adcap general description MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor general description 33 non-disclosure agreement required 1.5 pin assignments figure 1-2 shows the qfp pin assignments. figure 1-2. qfp pin assignments ptc1/atd9 pta2 v ss ptc0/atd8 ptb7/atd7 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 v ddad /v ddaref v ssad v refl v adcap ptc2 ptc3 ptc4 ptc5 irq1 /v pp ptf5/txd ptf4/rxd ptf3/miso ptf2/mosi ptf1/ss ptf0/spsck v dd pte7/tch3b pte6/tch2b pte5/tch1b pte4/tch0b pte3/tclkb pte2/tch1a pte1/tch0a pta1 pta0 v ssa osc2 osc1 cgmxfc v dda rst ptb1/atd1 ptb0/atd0 pta7 pta6 pta5 pta4 pta3 ptd1/fault2 ptc6 ptd0/fault1 ptd2/fault3 ptd3/fault4 ptd4/is1 ptd5/is2 ptd6/is3 pwm1 pwm2 pwm3 pwm4 pte0/tclka 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pwmgnd pwm5 pwm6 non-disclosure agreement required general description technical data MC68HC708MP16 ? rev. 3.1 34 general description freescale semiconductor 1.5.1 power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to preven t noise problems, take special care to provide power suppl y bypassing at the mcu as figure 1-3 shows. place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response cerami c capacitor for c1. c2 is an optional bulk current bypa ss capacitor for use in appl ications that require the port pins to sour ce high current levels. figure 1-3. power supply bypassing 1.5.2 oscillator pins (osc1 and osc2) the osc1 and osc2 pins ar e the connections for the on-chip oscillator circuit. (see section 8. clock g enerator module (cgm) .) 1.5.3 external reset pin (rst ) a logic 0 on the rst pin forces the mcu to a known start-up state. rst is bidirectional, allowing a reset of t he entire system. it is driven low when mcu v dd c2 c1 0.1 f v ss v dd + note: component values shown represent typical applications. general description MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor general description 35 non-disclosure agreement required any internal reset sour ce is asserted. (see section 7. system integration module (sim) .) 1.5.4 external interrupt pin (irq1 /v pp ) irq1 /v pp is an asynchronous extern al interrupt pin. (see section 17. external interrupt (irq) .) irq1 /v pp is also the eprom/otprom programming power pin. (see section 2. memory map .) 1.5.5 cgm power supply pins (v dda and v ssa ) v dda and v ssa are the power supply pins for the analog portion of the clock generator module (cgm). decoupl ing of these pins should be as per the digital supply. (see section 8. clock generator module (cgm) .) 1.5.6 external filter capacitor pin (cgmxfc) cgmxfc is an external filter capacito r connection for the cgm. (see section 8. clock gene rator module (cgm) .) 1.5.7 analog power supply pins (v ddad /v ddaref and v ssad ) v ddad /v ddaref and v ssad are the power supply pins for the analog-to- digital converter.decoupling of these pins should be as per the digital supply. (see section 19. analog-to-d igital conver ter (adc) .) 1.5.8 adc voltage decoupling capacitor pin (v adcap ) v adcap is one of two reference supp lies and is gener ated from v ddaref with a value (v ddaref ) /2. place a bypass capac itor on this pin to decouple noise. (see section 19. analog-to -digital converter (adc) .) non-disclosure agreement required general description technical data MC68HC708MP16 ? rev. 3.1 36 general description freescale semiconductor 1.5.9 adc voltage reference low pin (v refl ) v refl is the lower reference supp ly for the adc. connect the v refl pin to the same voltage potential as v ssa . (see section 19. analog-to- digital converter (adc) .) 1.5.10 port a input/output (i/o) pins (pta7 ? pta0) pta7?pta0 are general-purpose bidi rectional i/o port pins. (see section 15. input/output (i/o) ports .) 1.5.11 port b i/o pins (ptb7/atd7?ptb0/atd0) port b is an 8-bit special function port that shares all eight pins with the analog-to-digital conv ertor (adc). (see section 19. analog-to-digital converter (adc) and section 15. input/o utput (i/o) ports .) 1.5.12 port c i/o pins (ptc6?ptc2 and ptc1/atd9?ptc0/atd8) ptc6?ptc2 are general-purpose bidi rectional i/o port pins. (see section 15. input/output (i/o) ports .) ptc1/atd9 ? ptc0/atd8 are special function port pi ns that are shared with the analog-to-digital convertor (adc). (see section 19. analog-to-d igital converter (adc) and section 15. input/output (i/o) ports .) 1.5.13 port d input-only pins (ptd6/is3 ?ptd4/is1 and ptd3/fault4?ptd0/fault1) ptd6/is3 ?ptd4/is1 are special function input-o nly port pins that also serve as current sensing pins fo r the pulse width modulator module (pwmmc). ptd3/fault4?ptd0/fault1 are special function port pins that also serve as f ault pins for the pulse width modulator module (pwmmc). (see section 9. pulse width m odulator for motor control (pwmmc) and section 15. input/o utput (i/o) ports .) general description MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor general description 37 non-disclosure agreement required 1.5.14 pwm pins (pwm6?pwm1) pwm6 ? pwm1 are dedicated pins used for the outputs of the pulse width modulator module (pwmmc ). these are high curr ent pins capable of 20 ma sink (v ol = 0.8 v) and 7 ma (v oh =v dd ?0.8 v) source. (see section 9. pulse width modulat or for motor control (pwmmc) and section 21. electri cal specifications .) 1.5.15 pwm ground pin (pwmgnd) pwmgnd is the ground pin for the pulse widt h modulator module (pwmmc). this dedicated ground pin is used as the ground for the six high current pwm pins. (see section 9. pulse wi dth modulator for motor control (pwmmc) .) 1.5.16 port e i/o pins (pte7/tch3b?pte3/tclkb and pte2/tch1a?pte0/tclka) port e is an 8-bit special function port that shares its pins with the two timer interface modules (tima and timb). (see section 11. timer interface module a (tima) , section 12. timer interface module b (timb) , and section 15. input/output (i/o) ports .) 1.5.17 port f i/o pins (ptf5/txd?ptf4/rxd and ptf3/miso?ptf0/spsck) port f is a 6-bit special function port t hat shares two of its pins with the serial communications interface modu le (sci) and four of its pins with the serial peripheral inte rface module (spi). (see section 13. serial peripheral interf ace module (spi) , section 14. serial communications interface module (sci) , and section 15. input/output (i/o) ports .) non-disclosure agreement required general description technical data MC68HC708MP16 ? rev. 3.1 38 general description freescale semiconductor MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor memory map 39 non-disclosure agreement required technical data ? MC68HC708MP16 section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.4 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2.2 introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 16 kbytes of eprom or otprom 512 bytes of ram 46 bytes of user-defined vectors 240 bytes of monitor rom non-disclosure agreement required memory map technical data MC68HC708MP16 ? rev. 3.1 40 memory map freescale semiconductor $0000 i/o registers (96 bytes) $004f $0050 ram (512 bytes) $024f $0250 unimplemented (48,048 bytes) $bdff $be00 eprom (16,384 bytes) $fdff $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 reserved $fe05 reserved $fe06 reserved $fe07 eprom control register (epmcr) $fe08 unimplemented $fe09 unimplemented $fe0a unimplemented $fe0b pll control register $fe0c pll bandwidth control register $fe0d pll programming and control register $fe0e unimplemented $fe0f lvi status register (lvisr) $fe10 monitor rom (240 bytes) $feff $ff00 unimplemented (192 bytes) $ffbf $ffc0 reserved (18 bytes) $ffd1 $ffd2 vectors (46 bytes) $ffff figure 2-1. memory map memory map MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor memory map 41 non-disclosure agreement required 2.3 input/output (i/o) section addresses $0000?$004f, shown in figure 2-2 , contain most of the control, status, and data registers. additional i/o registers have these addresses: $fe00 ? sim break st atus register, sbsr $fe01 ? sim reset st atus register, srsr $fe03 ? sim break flag control register, sbfcr $fe07 ? eprom cont rol register, epmcr $fe0b ? pll control register $fe0c ? pll bandwid th control register $fe0d ? pll progr amming register $fe0f ? lvi status register, lvisr $ffff ? cop contro l register, copctl non-disclosure agreement required memory map technical data MC68HC708MP16 ? rev. 3.1 42 memory map freescale semiconductor ) addr. name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (pta) see page 320 . read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 322 . read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 324 . read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) see page 326 . read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 port e data register (pte) see page 328 . read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0005 port f data register (ptf) see page 330 . read: 0 0 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset $0006 data direction register a (ddra) see page 320 . read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 0 0 0 0 0 0 0 $0007 data direction register b (ddrb) see page 322 . read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 0 0 0 0 0 0 0 0 $0008 data direction register c (ddrc) see page 325 . read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 0 0 0 0 0 0 0 0 $0009 unimplemented read: write: x = indeterminate u = unaffected = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 1 of 9) memory map MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor memory map 43 non-disclosure agreement required $000a data direction register e (ddre) see page 329 . read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 0 0 0 0 0 0 0 0 $000b data direction register f (ddrf) see page 331 . read: 0 0 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset: 0 0 0 0 0 0 0 0 $000c timer a status and control register (tasc) see page 215 . read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 0 0 1 0 0 0 0 0 $000d timer a counter register high (tacnth) see page 217 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $000e timer a counter register low (tacntl) see page 217 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $000f timer a modulo register high (tamodh) see page 218 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0010 timer a modulo register low (tamodl) see page 218 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0011 timer a channel 0 status and control register (tasc0) see page 219 . read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 $0012 timer a channel 0 register high (tach0h) see page 223 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0013 timer a channel 0 register low (tach0l) see page 223 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset addr. name bit 7 6 5 4 3 2 1 bit 0 x = indeterminate u = unaffected = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 2 of 9) non-disclosure agreement required memory map technical data MC68HC708MP16 ? rev. 3.1 44 memory map freescale semiconductor $0014 timer a channel 1 status and control register (tasc1) see page 223 . read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 0 0 0 0 0 0 0 0 $0015 timer a channel 1 register high (tach1h) see page 223 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0016 timer a channel 1 register low (tach1l) see page 223 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0017 adc status and control register (adscr) read: coco/ idmas aien adco adch4 adch3 adch2 adch1 adch0 write: reset: 0 0 0 0 0 0 0 0 $0018 unimplemented read: write: $0019 adc data register (adr) see page 363 . read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: 0 0 0 0 0 0 0 0 $001a adc clock register (adclk) see page 363 . read: adiv2 adiv1 adiv0 adclk 0000 write: reset: 0 0 0 0 0 0 0 0 $001b spi control register (spcr) see page 277 . read: sprie dmas spmstr cpol cpha spwom spe sptie write: reset: 0 0 1 0 1 0 0 0 $001c spi status and control register (spscr) see page 279 . read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset: 0 0 0 0 1 0 0 0 $001d spi data register (spdr) see page 282 . read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset addr. name bit 7 6 5 4 3 2 1 bit 0 x = indeterminate u = unaffected = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 3 of 9) memory map MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor memory map 45 non-disclosure agreement required $001e irq status and control register (iscr) see page 345 . read: 0 0 0 0 irq1f 0 imask1 mode1 write: ack1 reset: 0 0 0 0 0 0 0 0 $001f configuration write-once register (config) see page 60 . read: edge botneg topneg indep lvirst lvipwr bit 1 copd write: reset: 0 0 0 0 0 0 0 0 $0020 pwm control register 1 (pctl1) see page 175 . read: disx disy pwmint pwmf isens1 isens0 ldok pwmen write: reset: 0 0 0 0 0 0 0 0 $0021 pwm control register 2 (pctl2) see page 177 . read: ldfq1 ldfq0 0 ipol1 ipol2 ipol3 prsc1 prsc0 write: reset: 0 0 0 0 0 0 0 0 $0022 fault control register (fcr) see page 180 . read: fint4 fmode4 fint3 fmode3 fint2 fmode2 fint1 fmode1 write: reset: 0 0 0 0 0 0 0 0 $0023 fault status register (fsr) see page 183 . read: fpin4 fflag4 fpin3 ffla g3 fpin2 fflag2 fpin1 fflag1 write: reset: u 0 u 0 u 0 u 0 $0024 fault acknowledge register (ftack) see page 185 . read: 0 0 dt6 dt5 dt4 dt3 dt2 dt1 write: ftack4 ftack3 ftack2 ftack1 reset: 0 0 0 0 0 0 0 0 $0025 pwm output control (pwmout) see page 186 . read: 0 outctl out6 out5 out4 out3 out2 out1 write: reset: 0 0 0 0 0 0 0 0 $0026 pwm counter register high (pcnth) see page 172 . read: 0 0 0 0 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0027 pwm counter register low (pcntl) see page 172 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 addr. name bit 7 6 5 4 3 2 1 bit 0 x = indeterminate u = unaffected = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 4 of 9) non-disclosure agreement required memory map technical data MC68HC708MP16 ? rev. 3.1 46 memory map freescale semiconductor $0028 pwm counter modulo register high (pmodh) see page 173 . read: 0 0 0 0 11 10 9 bit 8 write: reset: 0 0 0 0 x x x x $0029 pwm counter modulo register low (pmodl) see page 173 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: x x x x x x x x $002a pwm 1 value register high (pval1h) see page 174 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002b pwm 1 value register low (pval1l) see page 174 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $002c pwm 2 value register high (pval2h) see page 174 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002d pwm 2 value register low (pval2l) see page 174 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $002e pwm 3 value register high (pval3h) see page 174 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002f pwm 3 value register low (pval3l) see page 174 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0030 pwm 4 value register high (pval4h) see page 174 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0031 pwm 4 value register low (pval4l) see page 174 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 addr. name bit 7 6 5 4 3 2 1 bit 0 x = indeterminate u = unaffected = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 5 of 9) memory map MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor memory map 47 non-disclosure agreement required $0032 pwm 5 value register high (pval5h) see page 174 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0033 pwm 5 value register low (pval5l) see page 174 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0034 pwm 6 value register high (pval6h) see page 174 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0035 pwm 6 value register low (pval6l) see page 174 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0036 dead time write-once register (deadtm) see page 179 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0037 pwm disable mapping write- once register (dismap) see page 180 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0038 sci control register 1 (scc1) see page 301 . read: loops ensci txinv m wake ilty pen pty wfite: reset: 0 0 0 0 0 0 0 0 $0039 sci control register 2 (scc2) see page 304 . read: sctie tcie scrie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $003a sci control register 3 (scc3) see page 307 . read: r8 t8 00 orie neie feie peie write: reset: u u 0 0 0 0 0 0 $003b sci status register 1 (scs1) see page 309 . read: scte tc scrf idle or nf fe pe write: reset: 1 1 0 0 0 0 0 0 addr. name bit 7 6 5 4 3 2 1 bit 0 x = indeterminate u = unaffected = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 6 of 9) non-disclosure agreement required memory map technical data MC68HC708MP16 ? rev. 3.1 48 memory map freescale semiconductor $003c sci status register 2 (scs2) see page 313 . read: bkf rpf write: reset: 0 0 0 0 0 0 0 0 $003d sci data register (scdr) see page 314 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: unaffected by reset $003e sci baud rate register (scbr) see page 314 . read: scp1 scp0 r scr2 scr1 scr0 write: reset: 0 0 0 0 0 0 0 0 $003f timer b status and control register (tbsc) see page 240 . read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 0 0 1 0 0 0 0 0 $0040 timer b counter register high (tbcnth) see page 242 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0041 timer b counter register low (tbcntl) see page 242 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0042 timer b counter modulo register high (tbmodh) see page 243 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0043 timer b counter modulo register low (tbmodl) see page 243 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0044 timer b channel 0 status and control register (tbsc0) see page 244 . read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 $0045 timer b channel 0 register high (tbch0h) see page 248 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset addr. name bit 7 6 5 4 3 2 1 bit 0 x = indeterminate u = unaffected = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 7 of 9) memory map MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor memory map 49 non-disclosure agreement required $0046 timer b channel 0 register low (tbch0l) see page 248 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0047 timer b channel 1 status and control register (tbsc1) see page 244 . read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 0 0 0 0 0 0 0 0 $0048 timer b channel 1 register high (tbch1h) see page 248 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0049 timer b channel 1 register low (tbch1l) see page 248 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $004a timer b channel 2 status and control register (tbsc2) see page 244 . read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 0 0 0 0 0 0 0 0 $004b timer b channel 2 register high (tbch2h) see page 248 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $004c timer b channel 2 register low (tbch2l) see page 248 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $004d timer b channel 3 status and control register (tbsc3) see page 244 . read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset: 0 0 0 0 0 0 0 0 $004e timer b channel 3 register high (tbch3h) see page 248 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $004f timer b channel 3 register low (tbch3l) see page 248 . read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset addr. name bit 7 6 5 4 3 2 1 bit 0 x = indeterminate u = unaffected = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 8 of 9) non-disclosure agreement required memory map technical data MC68HC708MP16 ? rev. 3.1 50 memory map freescale semiconductor $fe00 sim break status register (sbsr) see page 99 . read: rr r r r r sbsw r write: note note: writing a logic 0 clears sbsw. reset: 0 $fe01 sim reset status register (srsr) see page 101 . read: por pin cop ilop ilad 0 lvi 0 write: reset: 1 0 0 0 0 0 0 0 $fe03 sim break flag control register (sbfcr) see page 102 . read: bcfe r r r r r r r write: reset: 0 $fe07 eprom control register (epmcr) see page 56 . read: 0 0 0 0 0 elat 0 epgm write: reset: 0 0 0 0 0 0 0 0 $fe0b pll control register (pctl) see page 117 . read: pllie pllf pllon bcs 1111 write: reset: 0 0 1 0 1 1 1 1 $fe0c pll bandwidth control register (pbwc) see page 119 . read: auto lock acq xld 0000 write: reset: 0 0 0 0 0 0 0 0 $fe0d pll programming register (ppg) see page 121 . read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 0 1 1 0 0 1 1 0 $fe0f lvi status register (lvisr) see page 350 . read: lviout 0 0 0 0 0 0 0 write: reset: 0 0 0 0 0 0 0 0 $ffff cop control register (copctl) see page 336 . read: low byte of reset vector write: writing to $ffff clears cop counter reset: unaffected by reset addr. name bit 7 6 5 4 3 2 1 bit 0 x = indeterminate u = unaffected = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 9 of 9) memory map MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor memory map 51 non-disclosure agreement required table 2-1 is a list of vector locations. table 2-1. vector addresses address vector low $ffd2 sci transmit vector (high) $ffd3 sci transmit vector (low) $ffd4 sci receive vector (high) $ffd5 sci receive vector (low) $ffd6 sci error vector (high) $ffd7 sci error vector (low) $ffd8 spi transmit vector (high) $ffd9 spi transmit vector (low) $ffda spi receive vector (high) $ffdb spi receive vector (low) $ffdc a/d vector (high) $ffdd a/d vector (low) $ffde tim a overflow vector (high) $ffdf tim a overflow vector (low) $ffe0 tim a channel 1 vector (high) $ffe1 tim a channel 1 vector (low) $ffe2 tim a channel 0 vector (high) $ffe3 tim a channel 0 vector (low) $ffe4 tim b overflow vector (high) $ffe5 tim b overflow vector (low) $ffe6 tim b channel 3 vector (high) $ffe7 tim b channel 3 vector (low) $ffe8 tim b channel 2 vector (high) $ffe9 tim b channel 2 vector (low) $ffea tim b channel 1 vector (high) $ffeb tim b channel 1 vector (low) $ffec tim b channel 0 vector (high) $ffed tim b channel 0 vector (low) $ffee pwm vector (high) $ffef pwm vector (low) priority non-disclosure agreement required memory map technical data MC68HC708MP16 ? rev. 3.1 52 memory map freescale semiconductor 2.4 monitor rom the 240 bytes at addresses $fe 10?$feff are reserved rom addresses that contain the instructi ons for the monitor functions. (see section 10. monitor rom (mon) .) $fff0 fault 4 (high) $fff1 fault 4 (low) $fff2 fault 3 (high) $fff3 fault 3 (low) $fff4 fault 2 (high) $fff5 fault 2 (low) $fff6 fault 1 (high) $fff7 fault 1 (low) $fff8 pll vector (high) $fff9 pll vector (low) $fffa irq1 vector (high) $fffb irq1 vector (low) $fffc swi vector (high) $fffd swi vector (low) high $fffe reset vector (high) $ffff reset vector (low) table 2-1. vector addresses (continued) address vector priority MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor random-access memory (ram) 53 non-disclosure agreement required technical data ? MC68HC708MP16 section 3. random-access memory (ram) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.2 introduction this section describes the 512 bytes of ram. 3.3 functional description addresses $0050?$024f are ram locati ons. the location of the stack ram is programmable. the 16-bit stack pointer a llows the stack to be anywhere in the 64-kb yte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 160 bytes of ra m. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff, dire ct addressing mode instructions can access efficiently all page zero ram locations. pa ge zero ram, therefore, provides ideal locati ons for frequently accessed global variables. before processing an interrupt, the cp u uses five bytes of the stack to save the contents of the cpu registers. note: for m6805 compatibility, the h register is not stacked. non-disclosure agreement required random-access memory (ram) technical data MC68HC708MP16 ? rev. 3.1 54 random-access memory (ram) freescale semiconductor during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack po inter decrements during pushes and increments during pulls. note: be careful when using nested subr outines. the cpu ma y overwrite data in the ram during a s ubroutine or during the interrupt stacking operation. MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor eprom/otprom 55 non-disclosure agreement required technical data ? MC68HC708MP16 section 4. eprom/otprom 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.4 eprom/otprom control r egister. . . . . . . . . . . . . . . . . . . . .56 4.5 eprom/otprom progra mming sequence . . . . . . . . . . . . . . 57 4.2 introduction this section describes the non-volatile memory (eprom/otprom). 4.3 functional description an mcu with a quartz window has 16 kbytes of erasable, programmable rom (eprom). the quartz window allows ep rom erasure by using ultraviolet light. in an mcu wit hout the quartz wi ndow, the eprom cannot be erased and serves as 16 kb ytes of one-time programmable rom (otprom). an unprogrammed or erased location reads as $00. the following addresses are user eprom/otprom locations: $be00?$fdff $ffd2?$ffff (these locations are reserved for user-defined interrupt and reset vectors.) programming tools are available from freescale. contact your local freescale representative for more information. note: a security feature prevents view ing of the eprom /otprom contents. 1 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the eprom/otprom diff icult for unauthorized users. non-disclosure agreement required eprom/otprom technical data MC68HC708MP16 ? rev. 3.1 56 eprom/otprom freescale semiconductor 4.4 eprom/otprom control register the eprom control register cont rols eprom/otprom programming. elat ? eprom/otprom latch control bit this read/write bit latches the address and data buses for programming the eprom/ otprom. clearing elat also clears the epgm bit. eprom/otprom data cannot be read when elat is set. 1 = buses configured for eprom/otprom programming 0 = buses configured for normal operation epgm ? eprom/otprom program control bit this read/write bit appl ies the programming voltage from the irq1 /v pp pin to the eprom/otprom. to write to the epgm bit, the elat bit must be set already . reset clears the epgm bit. 1 = eprom/otprom program ming power switched on 0 = eprom/otprom program ming power switched off address: $fe07 $fe07 bit 7654321bit 0 read: 00000 elat 0 epgm write: reset: 00000000 = unimplemented figure 4-1. eprom/otprom control register (epmcr) eprom/otprom MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor eprom/otprom 57 non-disclosure agreement required 4.5 eprom/otprom programming sequence the unprogrammed state is a 0. progr amming changes the state to a 1. use the following proc edure to program a by te of eprom/otprom: 1. apply v dd + v hi to the irq1 /v pp pin. 2. set the elat bit. note: writing logic 1s to both the elat and epgm bits with a single instruction sets only the elat bit. epgm must be set by a separate instruction in the programming sequence. 3. write to any user eprom/ot prom address. note: writing to an invalid address prev ents the programming voltage from being applied. 4. set the epgm bit. 5. wait for a time, t epgm . 6. clear the elat and epgm bits. setting the elat bit configures the address and data buses to latch data for programming the array. only data written to a valid eprom address will be latched. attempts to read any other valid ep rom address after step 2 will read the latch ed data written in step 3. further writes to valid eprom addresses after the firs t write (step 3) are ignored. the epgm bit cannot be se t if elat bit is clea red. this is to ensure proper programming sequenc e. if epgm is set and a valid eprom write occurred, v pp will be applied to the user eprom array. when the epgm bit is cleared, the program volt age is removed from the array. non-disclosure agreement required eprom/otprom technical data MC68HC708MP16 ? rev. 3.1 58 eprom/otprom freescale semiconductor MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor configuration register (config) 59 non-disclosure agreement required technical data ? MC68HC708MP16 section 5. configuration register (config) 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 5.2 introduction this section describe s the configuration register (config). this register contains bits that confi gure the following options: resets caused by the lvi module power to the lvi module computer operating pr operly module (cop) top-side pwm polarity bottom-side pwm polarity edge-aligned versus center-aligned pwms six independent pwms versus th ree complementary pwm pairs non-disclosure agreement required configuration register (config) technical data MC68HC708MP16 ? rev. 3.1 60 configuration register (config) freescale semiconductor 5.3 functional description the configuration register is a writ e-once register. ou t of reset, the configuration register will read all 0s. once the regist er is written, further writes will have no e ffect until a reset occurs. note: if the lvi module and the lvi rese t signal are enabled, a reset occurs when v dd falls to a voltage, lvi tripf , and remains at or below that level for at least nine cons ecutive cpu cycles. once an lvi reset occurs, the mcu remains in reset until v dd rises to a voltage, lvi tripr . edge ? edge- align enable bit edge determines if the motor c ontrol pwm will operate in edge- aligned mode or center -aligned mode. (see section 9. pulse width modulator for moto r control (pwmmc) .) 1 = edge-aligned mode enabled 0 = center-alig ned mode enabled botneg ? bottom-si de pwm polarity bit botneg determines if the bottom- side pwms will have positive or negative polarity. (see section 9. pulse widt h modulator for motor control (pwmmc) .) 1 = negative polarity 0 = positive polarity topneg ? top-side pwm polarity bit topneg determines if the top-si de pwms will have positive or negative polarity. (see section 9. pulse widt h modulator for motor control (pwmmc) .) 1 = negative polarity 0 = positive polarity $001fbit 7654321bit 0 read: edge botneg topneg indep lvirst lvipwr bit 1 copd write: reset:00000000 figure 5-1. configurat ion register (config) configuration register (config) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor configuration register (config) 61 non-disclosure agreement required indep ? independent mode enable bit indep determines if t he motor control pwms will be six independent pwms or three complem entary pwm pairs. (see section 9. pulse width modulator for mo tor control (pwmmc) .) 1 = six independent pwms 0 = three complementary pwm pairs lvipwr ? lvi power disable bit lvipwr disables th e lvi module. (see section 18. low-voltage inhibit (lvi) .) 1 = lvi module power disabled 0 = lvi module power enabled lvirst ? lvi reset disable bit lvirst disables the reset sig nal from the lvi module. (see section 18. low-voltage inhibit (lvi) .) 1 = lvi module resets disabled 0 = lvi module resets enabled copd ? cop disable bit copd disables the cop module. (see section 16. computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled non-disclosure agreement required configuration register (config) technical data MC68HC708MP16 ? rev. 3.1 62 configuration register (config) freescale semiconductor MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor central processor unit (cpu) 63 non-disclosure agreement required technical data ? MC68HC708MP16 section 6. central processor unit (cpu) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.4.1 accumulator (a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.4.2 index register (h:x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.4.3 stack pointer (sp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.4.4 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.4.5 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . 69 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2 introduction this section describes the central processor unit (cpu08, version a). the m68hc08 cpu is an enhanced and fully object-code-compatible version of the m68hc05 cpu. the cpu08 reference manual (freescale document num ber cpu08rm/ad) contai ns a description of the cpu instru ction set, addressing modes, and architecture. non-disclosure agreement required central processor unit (cpu) technical data MC68HC708MP16 ? rev. 3.1 64 central processor unit (c pu) freescale semiconductor 6.3 features features of the cpu include the following: full upward, object- code compatibility wi th m68hc05 family 16-bit stack pointer with st ack manipulation instructions 16-bit index register with x-re gister manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decim al (bcd) data handling modular architecture with exp andable internal bu s definition for extension of addressi ng range beyond 64 kbytes low-power wait mode 6.4 cpu registers figure 6-1 shows the five cpu registers. cpu regist ers are not part of the memory map. central processor unit (cpu) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor central processor unit (cpu) 65 non-disclosure agreement required figure 6-1. cpu registers 6.4.1 accumulator (a) the accumulator is a general-purpose 8- bit register. the cpu uses the accumulator to hold operands and th e results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a) non-disclosure agreement required central processor unit (cpu) technical data MC68HC708MP16 ? rev. 3.1 66 central processor unit (c pu) freescale semiconductor 6.4.2 index register (h:x) the 16-bit index register allows indexed addressing of a 64-kbyte memory space. h is the upper byte of the index regi ster, and x is the lower byte. h:x is the conc atenated 16-bit index register. in the indexed addressi ng modes, the cpu uses the contents of the index register to determine the conditional addr ess of the operand. the index register can serve also as a temporary data storage location. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: write: reset:0 0 0 0 0 0 0 0xxxxxxxx x = indeterminate figure 6-3. index register (h:x) central processor unit (cpu) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor central processor unit (cpu) 67 non-disclosure agreement required 6.4.3 stack pointer (sp) the stack pointer is a 16-bi t register that contains the address of the next location on the stack. during a rese t, the stack pointer is preset to $00ff. the reset stack pointer (rsp ) instruction sets the least significant byte to $ff and does not af fect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bi t offset and 16-bit offs et addressing modes, the stack pointer can functi on as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note: the location of the stack is arbitr ary and may be relocated anywhere in ram. moving the sp out of page zero ($0000 to $00ff) frees direct address (page zero) space. for correct operation, the stack pointer must point only to ram locations. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: write: reset:0000000011111111 figure 6-4. stack pointer (sp) non-disclosure agreement required central processor unit (cpu) technical data MC68HC708MP16 ? rev. 3.1 68 central processor unit (c pu) freescale semiconductor 6.4.4 program counter (pc) the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter autom atically increm ents to the next sequential memory location every time an instruct ion or operand is fetched. jump, branch, and interr upt operations l oad the program counter with an addr ess other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vect or address is the address of the first instruction to be executed after exiti ng the reset state. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. prog ram counter (pc) central processor unit (cpu) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor central processor unit (cpu) 69 non-disclosure agreement required 6.4.5 condition code register (ccr) the 8-bit condition code register cont ains the interrupt mask and five flags that indicate the re sults of the instruction just executed. bits 6 and 5 are set permanently to logic one. the following pa ragraphs describe the functions of the c ondition code register. v ? overflow flag the cpu sets the overfl ow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry fl ag when a carry occurs between accumulator bits 3 and 4 during an add or adc o peration. the half- carry flag is required for binary- coded decimal (bcd ) arithmetic operations. the daa instru ction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 bit 76 5 4 3 2 1bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 6-6. condition code register (ccr) non-disclosure agreement required central processor unit (cpu) technical data MC68HC708MP16 ? rev. 3.1 70 central processor unit (c pu) freescale semiconductor i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are ena bled when the interrupt mask is cleared. when a cpu in terrupt occurs, the interrupt mask is set automatically after t he cpu registers are sa ved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 compatibility, the upper byte of the i ndex register (h) is not stacked automatical ly. if the interrupt serv ice routine modifies h, then the user must st ack and unstack h using the pshh and pulh instructions. after the i bit is clear ed, the highest-priority interrupt request is serviced first. a return from interrupt (rti) instru ction pulls the cp u registers from the stack and restores the interr upt mask from the stack. after any reset, the interrupt mask is set and can only be cleared by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmet ic operation, logic operation, or data manipul ation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulati on produces a result of $00. 1 = zero result 0 = non-zero result central processor unit (cpu) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor central processor unit (cpu) 71 non-disclosure agreement required c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of th e accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 6.5 arithmetic/l ogic unit (alu) the alu performs the arit hmetic and logic operat ions defined by the instruction set. refer to the cpu08 reference manual (freescale document number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about cpu architecture. non-disclosure agreement required central processor unit (cpu) technical data MC68HC708MP16 ? rev. 3.1 72 central processor unit (c pu) freescale semiconductor 6.6 instruction set summary table 6-1 provides a summary of t he m68hc08 instruction set. table 6-1. instr uction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ? ?? ??? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 c b0 b7 0 b0 b7 c central processor unit (cpu) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor central processor unit (cpu) 73 non-disclosure agreement required bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc non-disclosure agreement required central processor unit (cpu) technical data MC68HC708MP16 ? rev. 3.1 74 central processor unit (c pu) freescale semiconductor bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor central processor unit (cpu) 75 non-disclosure agreement required cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? ?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ? ?? ??? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? ??? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? ?? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc non-disclosure agreement required central processor unit (cpu) technical data MC68HC708MP16 ? rev. 3.1 76 central processor unit (c pu) freescale semiconductor inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ? ??0 ?? dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 central processor unit (cpu) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor central processor unit (cpu) 77 non-disclosure agreement required neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ? ?? ??? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp ) ? 1 ??????inh 87 2 pshh push h onto stack push (h) ; sp (sp ) ? 1 ??????inh 8b 2 pshx push x onto stack push (x) ; sp (sp ) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ? ?? ??? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ? ?? ??? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ?????? inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c non-disclosure agreement required central processor unit (cpu) technical data MC68HC708MP16 ? rev. 3.1 78 central processor unit (c pu) freescale semiconductor sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ?? ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) ?????? inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor central processor unit (cpu) 79 non-disclosure agreement required 6.7 opcode map see table 6-2 . tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ?? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location ? set or cleared n negative bit ? not affected table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc non-disclosure agreement required technical data MC68HC708MP16 ? rev. 3.1 80 central processor unit (cpu) freescale semiconductor central processor unit (cpu) table 6-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789abcd9ede9eef 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4sp2 3 sub 2ix1 4 sub 3sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4sp2 3 cmp 2ix1 4 cmp 3sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4sp2 3 sbc 2ix1 4 sbc 3sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4sp2 3 cpx 2ix1 4 cpx 3sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4sp2 3 and 2ix1 4 and 3sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4sp2 3 bit 2ix1 4 bit 3sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4sp2 3 lda 2ix1 4 lda 3sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4sp2 3 sta 2ix1 4 sta 3sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4sp2 3 eor 2ix1 4 eor 3sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4sp2 3 adc 2ix1 4 adc 3sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4sp2 3 ora 2ix1 4 ora 3sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4sp2 3 add 2ix1 4 add 3sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4sp2 3 ldx 2ix1 4 ldx 3sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4sp2 3 stx 2ix1 4 stx 3sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor system integration module (sim) 81 non-disclosure agreement required technical data ? MC68HC708MP16 section 7. system integration module (sim) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 85 7.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.3.2 clock start-up from por or lvi reset . . . . . . . . . . . . . . . . 85 7.3.3 clocks in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.4 reset and system initializa tion. . . . . . . . . . . . . . . . . . . . . . . . . 86 7.4.1 external pin reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.4.2 active resets from inte rnal sources . . . . . . . . . . . . . . . . . . 88 7.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 7.4.2.2 computer operati ng properly (cop) reset. . . . . . . . . . . 90 7.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 7.4.2.5 low-voltage inhibit (l vi) reset . . . . . . . . . . . . . . . . . . . . 91 7.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . . 91 7.5.2 sim counter and reset st ates . . . . . . . . . . . . . . . . . . . . . . 91 7.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.6.3 status flag protection in break mode. . . . . . . . . . . . . . . . . 96 7.7 low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.7.2 sim break status regist er . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.7.3 sim reset status regi ster . . . . . . . . . . . . . . . . . . . . . . . . 101 7.7.4 sim break flag control register . . . . . . . . . . . . . . . . . . . 102 non-disclosure agreement required system integration module (sim) technical data MC68HC708MP16 ? rev. 3.1 82 system integration module (sim) freescale semiconductor 7.2 introduction this section describes the system in tegration module. together with the cpu, the sim controls all mcu activi ties. a block diagram of the sim is shown in figure 7-1 . figure 7-1 is a summary of the sim i/o registers. the sim is a system state controller t hat coordinates cpu and exception timing. the sim is responsible for: bus clock generation and cont rol for cpu and peripherals ? wait/reset/break entry and recovery ? internal clock control master reset control, includi ng power-on reset (por) and cop timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture exp andable to 128 interrupt sources system integration module (sim) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor system integration module (sim) 83 non-disclosure agreement required figure 7-1. sim block diagram wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module wait cpu wait (from cpu) simoscen (to cgm) cgmout (from cgm) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock cgmxclk (from cgm) 2 non-disclosure agreement required system integration module (sim) technical data MC68HC708MP16 ? rev. 3.1 84 system integration module (sim) freescale semiconductor table 7-1 shows the internal signal na mes used in this section. addr. name bit 7 6 5 4 3 2 1 bit 0 $fe00 sim break status register (sbsr) read: rr r r r r sbsw r write: note note: writing a logic 0 clears sbsw. reset: 0 $fe01 sim reset status register (srsr) read: por pin cop ilop ilad 0 lvi 0 write: reset: 1 0 0 0 0 0 0 0 $fe03 sim break flag control register (sbfcr) read: bcfe r r r r r r r write: reset: 0 figure 7-2. sim i/o register summary table 7-1. signal name conventions signal name description cgmxclk buffered version of osc1 from clock generator module (cgm) cgmvclk pll output cgmout pll-based or osc1-based clock output from cgm module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal system integration module (sim) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor system integration module (sim) 85 non-disclosure agreement required 7.3 sim bus clock control and generation the bus clock generator provides system clock signal s for the cpu and peripherals on the mcu. the syst em clocks are generated from an incoming clock, cg mout, as shown in figure 7-3 . this clock can come from either an external oscillat or or from the on-chip pll. (see section 8. clock generator module (cgm) .) figure 7-3. cgm clock signals 7.3.1 bus timing in user mode , the internal bus fr equency is either t he crystal oscillator output (cgmxclk) divided by four or the pll output (cgmvclk) divided by four. (see section 8. clock g enerator module (cgm) .) 7.3.2 clock start-up from por or lvi reset when the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripheral s are inactive and held in an inactive phase unt il after the 4096 cgmxclk cycle por timeout has completed. the rst pin is driven low by the sim during this entire period. the ibus clocks start upon comp letion of the timeout. pll osc1 cgmxclk 2 bus clock generators sim cgm sim counter ptc3 monitor mode clock select circuit cgmvclk bcs 2 a b s* cgmout *when s = 1, cgmout = b user mode non-disclosure agreement required system integration module (sim) technical data MC68HC708MP16 ? rev. 3.1 86 system integration module (sim) freescale semiconductor 7.3.3 clocks in wait mode in wait mode, t he cpu clocks are inactive. th e sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if t he module is active or i nactive in wait mode. some modules can be programmed to be active in wait mode. 7.4 reset and system initialization the mcu has the following reset sources: power-on reset module (por) external reset pin (rst ) computer operating pr operly module (cop) low-voltage inhi bit module (lvi) illegal opcode illegal address all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to thei r default values and all modules to be returned to thei r reset states. an internal reset clear s the sim counter (see 7.5 sim counter ), but an external reset does not. each of th e resets sets a co rresponding bit in the sim reset status register ( srsr). (see 7.7.3 sim reset status register .) system integration module (sim) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor system integration module (sim) 87 non-disclosure agreement required 7.4.1 external pin reset pulling the asynchronous rst pin low halts all pr ocessing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 cg mxclk cycles, assuming t hat neither the por nor the lvi was the sour ce of the reset. see table 7-2 for details. figure 7-4 shows the relative timing. figure 7-4. extern al reset timing table 7-2. pin bit set timing reset type number of cycles required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l cgmout non-disclosure agreement required system integration module (sim) technical data MC68HC708MP16 ? rev. 3.1 88 system integration module (sim) freescale semiconductor 7.4.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow resetting of external peripherals. the inte rnal reset signal irst continues to be assert ed for an additional 32 cycles. (see figure 7-5 .) an internal reset can be c aused by an illegal address, illegal opcode, cop timeout, lv i, or por. (see figure 7-6 .) note that for lvi or por resets, the si m cycles through 4096 cgmxclk cycles during which the sim forces the rst pin low. the inter nal reset signal then follows the sequence fr om the falling edge of rst shown in figure 7-5 . figure 7-5. inter nal reset timing the cop reset is asynchro nous to the bus clock. figure 7-6. sources of internal reset the active reset feature allows the par t to issue a reset to peripherals and other chips within a system built around the mcu. irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk illegal address rst illegal opcode rst coprst lvi por internal reset system integration module (sim) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor system integration module (sim) 89 non-disclosure agreement required 7.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pul se to indicate that pow er-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. sixty-four cg mxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, the foll owing events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables cgmout. internal clocks to the cpu and m odules are held i nactive for 4096 cgmxclk cycles to al low stabilization of the oscillator. the rst pin is driven low during th e oscillator stabilization time. the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared. figure 7-7. por recovery porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff non-disclosure agreement required system integration module (sim) technical data MC68HC708MP16 ? rev. 3.1 90 system integration module (sim) freescale semiconductor 7.4.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all intern al reset sources. to prevent a cop module timeout, wr ite any value to location $ffff. writing to location $ffff clears th e cop counter and bits 12 through 4 of the sim counter. the s im counter output, which o ccurs at least every 2 13 ? 2 4 cgmxclk cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time befor e the first timeout. the cop module is disabled if the rst pin or the irq1 /v pp pin is held at v dd +v hi while the mcu is in monito r mode. the cop module can be disabled only through co mbinational logic c onditioned with the high voltage signal on the rst or the irq1 /v pp pin. this prevents the cop from becoming disabled as a result of external noise. during a break state, v dd +v hi on the rst pin disables the cop module. 7.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bi t in the sim reset status register (srsr) and causes a reset. because the mc68hc708mp 16 has stop mode dis abled, execution of the stop instruction will c ause an illegal opcode reset. 7.4.2.4 illegal address reset an opcode fetch from addresses ot her than eprom or ram addresses generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. system integration module (sim) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor system integration module (sim) 91 non-disclosure agreement required 7.4.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit m odule (lvi) asserts its output to the sim when the v dd voltage falls to the lvi tripf voltage and remains at or below that level for at least nine consecutiv e cpu cycles. the lvi bit in the sim reset status register (srsr) is se t, and the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. sixty-four cgmxclk cycles later, t he cpu is released from reset to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 7.5 sim counter the sim counter is used by the power -on reset module (por) to allow the oscillator time to stabilize before enabling t he internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly module (cop). the sim counter overflow supplies the clock for the cop module. the sim counter is 13 bits long and is clocked by the fall ing edge of cgmxclk. 7.5.1 sim counter during power-on reset the power-on reset module (por) dete cts power appli ed to the mcu. at power-on, the por ci rcuit asserts the signal porrst. once the sim is initialized, it enabl es the clock generation m odule (cgm) to drive the bus clock state machine. 7.5.2 sim counter and reset states external reset has no effect on the sim counter. the sim counter is free- running after all re set states. (see 7.4.2 active resets from internal sources for counter control and inter nal reset recovery sequences.) non-disclosure agreement required system integration module (sim) technical data MC68HC708MP16 ? rev. 3.1 92 system integration module (sim) freescale semiconductor 7.6 exception control normal, sequential progra m execution can be chang ed in three different ways: interrupts ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts 7.6.1 interrupts at the beginning of an interrupt, the cpu sa ves the cpu register contents on the sta ck and sets the interrupt ma sk (i bit) to prevent additional interrupts. at the end of an interrupt , the rti instruction recovers the cpu regist er contents from the stack so that normal processing can resume. figure 7-8 shows interrupt entry timing. figure 7-10 shows interrupt recovery timing. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which ve ctor to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serv iced (or the i bit is cleared). (see figure 7-9 .) figure 7-8 . interrupt entry module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit system integration module (sim) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor system integration module (sim) 93 non-disclosure agreement required figure 7-9. interrupt processing no no no yes no no yes no yes yes as many interrupts as exist on chip i bit set? from reset break interrupt? i bit set? int0 interrupt? int11 interrupt? swi instruction? rti instruction? fetch next instruction. unstack cpu registers. stack cpu registers. set i bit. load pc with interrupt vector. execute instruction. yes yes non-disclosure agreement required system integration module (sim) technical data MC68HC708MP16 ? rev. 3.1 94 system integration module (sim) freescale semiconductor figure 7-10. in terrupt recovery 7.6.1.1 hardware interrupts a hardware interrupt does not stop the current in struction. processing of a hardware interrupt begins after completion of t he current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts ar e not masked (i bit clear in the condition code register), and if the corres ponding interrupt enable bit is set, the sim proceeds with interrup t processing; other wise, the next instruction is fetched and executed. if more than one interrupt is pending at th e end of an instruction execution, the highest priority interrupt is serviced first. figure 7-11 demonstrates what hap pens when two interrupts are pending. if an interrupt is pending upon exit from the original inte rrupt service routine, the pending interrupt is serviced before the lda in struction is executed. module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1[7:0] pc ? 1[15:8] opcode operand i bit system integration module (sim) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor system integration module (sim) 95 non-disclosure agreement required figure 7-11 . interrupt recognition example the lda opcode is pr efetched by both th e int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during in terrupt entry. if the in terrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prio r to exiting the routine. 7.6.1.2 swi instruction the swi instruction is a non-maskable instruct ion that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. cli lda int1 pulh rti int2 background routine #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine non-disclosure agreement required system integration module (sim) technical data MC68HC708MP16 ? rev. 3.1 96 system integration module (sim) freescale semiconductor 7.6.2 reset all reset sources always have equal and highest pr iority and cannot be arbitrated. 7.6.3 status flag protection in break mode the sim controls whether status fl ags contained in ot her modules can be cleared during break m ode. the user can sele ct whether flags are protected from being clea red by properly initiali zing the break clear flag enable bit (bcfe) in t he sim break flag contro l register (sbfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mo de without losing stat us flag information. setting the bcfe bit e nables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step cleari ng mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 7.7 low-power mode executing the wait instruction puts the mcu in a low-power- consumption mode for st andby situations. the s im holds the cpu in a non-clocked state. the operation of this mode is described below. wait clears the interrupt mask (i) in the condition code register, allowing interrupts to occur. system integration module (sim) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor system integration module (sim) 97 non-disclosure agreement required 7.7.1 wait mode in wait mode, t he cpu clocks are inactive while the peripheral clocks continue to run. figure 7-12 shows the timing fo r wait mode entry. a module that is active during wa it mode can wake up the cpu with an interrupt if the interrupt is enabled . stacking for the interrupt begins one cycle after the wait instruction dur ing which the inte rrupt occurred. refer to the wait mode su bsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if the cop disable bit, copd, in the configuration register is logic 0, then the comp uter operating properly module (cop) is enabled and remains active in wait mode. figure 7-12. wait mode entry timing wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. non-disclosure agreement required system integration module (sim) technical data MC68HC708MP16 ? rev. 3.1 98 system integration module (sim) freescale semiconductor figure 7-13 and figure 7-14 show the timing for wait recovery. figure 7-13. wait recovery from interrupt or break figure 7-14. wait recover y from internal reset $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclk 32 cycles 32 cycles system integration module (sim) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor system integration module (sim) 99 non-disclosure agreement required 7.7.2 sim break status register the sim break status register contains a flag to indica te that a break caused an exit from wait mode. sbsw ? sim break stop/wait this status bit is useful in applicati ons requiring a return to wait mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. reset clears sbsw. 1 = wait mode was exit ed by break interrupt. 0 = wait mode was not exit ed by break interrupt. sbsw can be read within the break state swi r outine. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example of this . writing zero to the sbsw bit clears it. address: $fe00 bit 7654321bit 0 read: rr5r r r r sbsw r write: note (1) reset: 0 r = reserved for factory test note 1. writing a logic 0 clears sbsw. figure 7-15. sim break st atus register (sbsr) non-disclosure agreement required system integration module (sim) technical data MC68HC708MP16 ? rev. 3.1 100 system integration module (sim) freescale semiconductor ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode was exited by break. tst lobyte,sp ; if returnlo is not zero, bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte, too. dolo dec lobyte,sp ; point to wait opcode. return pulh rti ; restore h register. system integration module (sim) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor system integration module (sim) 101 non-disclosure agreement required 7.7.3 sim reset status register this register contains six flags that show the sour ce of the last reset. clear the sim reset status register by reading it. a power-on reset sets the por bit and clear s all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operati ng properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address rese t bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr lvi ? low-voltage i nhibit reset bit 1 = last reset was caused by the lvi circuit 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad 0 lvi 0 write: por:10000000 = unimplemented figure 7-16. sim reset status register (srsr) non-disclosure agreement required system integration module (sim) technical data MC68HC708MP16 ? rev. 3.1 102 system integration module (sim) freescale semiconductor 7.7.4 sim break flag control register the sim break control regist er contains a bit that enables software to clear status bits while t he mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear st atus bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r = reserved for factory test figure 7-17. sim br eak flag control register (sbfcr) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor clock generator module (cgm) 103 non-disclosure agreement required technical data ? MC68HC708MP16 section 8. clock generator module (cgm) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 8.4.1 crystal oscillator circ uit . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.4.2 phase-locked loop circ uit (pll) . . . . . . . . . . . . . . . . . . . 107 8.4.2.1 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.4.2.2 acquisition and tracking modes . . . . . . . . . . . . . . . . . . 109 8.4.2.3 manual and automatic pll b andwidth modes . . . . . . . 109 8.4.2.4 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.4.2.5 special programming exceptions . . . . . . . . . . . . . . . . . 112 8.4.3 base clock selector circuit. . . . . . . . . . . . . . . . . . . . . . . . 112 8.4.4 cgm external connectio ns. . . . . . . . . . . . . . . . . . . . . . . . 113 8.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.5.1 crystal amplifier input pin (osc1) . . . . . . . . . . . . . . . . . . 114 8.5.2 crystal amplifier ou tput pin (osc2) . . . . . . . . . . . . . . . . . 114 8.5.3 external filter capacitor pin (c gmxfc). . . . . . . . . . . . . . 114 8.5.4 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . 115 8.5.5 oscillator enable signal (simoscen) . . . . . . . . . . . . . . . 115 8.5.6 crystal output frequency signal (cgmxclk) . . . . . . . . . 115 8.5.7 cgm base clock output (cgmout) . . . . . . . . . . . . . . . . 115 8.5.8 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . 116 8.6 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.6.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.6.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . 119 8.6.3 pll programming regist er . . . . . . . . . . . . . . . . . . . . . . . . 121 8.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 8.8 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.9 cgm during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 non-disclosure agreement required clock generator module (cgm) technical data MC68HC708MP16 ? rev. 3.1 104 clock generator module (cgm) freescale semiconductor 8.10 acquisition/lock time spec ifications . . . . . . . . . . . . . . . . . . . 124 8.10.1 acquisition/lock time definitions . . . . . . . . . . . . . . . . . . . 124 8.10.2 parametric influences on reaction time . . . . . . . . . . . . . 126 8.10.3 choosing a filter capac itor. . . . . . . . . . . . . . . . . . . . . . . . 127 8.10.4 reaction time calculat ion . . . . . . . . . . . . . . . . . . . . . . . . 127 8.2 introduction this section describes the clock generator m odule (cgm, version a). the cgm generates the crystal clock si gnal, cgmxclk, which operates at the frequency of the crystal. the cgm also generates the base clock signal, cgmout, from which the system integration module (sim) derives the system clocks. cgmout is based on either the crystal clock divided by two or the p hase-locked loop (pll) cl ock, cgmvclk, divided by two. the pll is a frequency generator design ed for use with crystals or ceramic resonators. the pll ca n generate an 8-mhz bus frequency without using a 32-mhz crystal. 8.3 features features of the cgm include the following: phase-locked loop with output freque ncy in integer multiples of the crystal reference programmable hardware voltage-c ontrolled oscillator (vco) for low-jitter operation automatic bandwidth control mode for low-jitt er operation automatic frequency lock detector cpu interrupt on entry or exit from locked condition clock generator module (cgm) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor clock generator module (cgm) 105 non-disclosure agreement required 8.4 functional description the cgm consists of three major submodules: crystal oscillator circuit ? the crystal osc illator circuit generates the constant crystal frequency clock, cgmxclk. phase-locked l oop (pll) ? the p ll generates the programmable vco fr equency clock cgmvclk. base clock selector circuit ? th is software-controlled circuit selects either cgmx clk divided by two or the vco clock, cgmvclk, divided by two as t he base clock, cgmout. the sim derives the system clocks from cgmout. figure 8-1 shows the struct ure of the cgm. 8.4.1 crystal oscillator circuit the crystal oscillator circuit consis ts of an inverting amplifier and an external crystal. the osc1 pin is t he input to the amp lifier and the osc2 pin is the output. the simoscen si gnal from the sys tem integration module (sim) enables the cr ystal oscillator circuit. the cgmxclk signal is t he output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. cg mxclk is then buffered to produce cgmrclk, t he pll reference clock. cgmxclk can be used by other modul es which require precise timing for operation. the duty cycl e of cgmxclk is not guaranteed to be 50% and depends on external factors, including t he crystal and related external components. an externally generated cl ock also can feed the os c1 pin of the crystal oscillator circuit. connect the exter nal clock to the o sc1 pin and let the osc2 pin float. non-disclosure agreement required clock generator module (cgm) technical data MC68HC708MP16 ? rev. 3.1 106 clock generator module (cgm) freescale semiconductor figure 8-1. cgm block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator bandwidth control lock detector clock cgmxclk cgmout cgmvdv cgmvclk simoscen crystal oscillator interrupt control cgmint cgmrdv pll analog 3 2 cgmrclk select circuit lock auto acq vrs[7:4] pllie pllf mul[7:4] cgmxfc v ss v dda osc1 osc2 to sim to sim ptc3 monitor mode a b s* user mode *when s = 1, cgmout = b clock generator module (cgm) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor clock generator module (cgm) 107 non-disclosure agreement required 8.4.2 phase-locked loop circuit (pll) the pll is a frequency gene rator that can operate in either acquisition mode or tracking mode, depending on the a ccuracy of the output frequency. the pll can change betw een acquisition and tracking modes either automat ically or manually. 8.4.2.1 pll circuits the pll consists of the following circuits: voltage-controlled oscillator (vco) modulo vco fr equency divider phase detector loop filter lock detector addr. name bit 7 6 5 4 3 2 1 bit 0 $fe0b pll control register (pctl) read: pllie pllf pllon bcs 1111 write: reset: 0 0 1 0 1 1 1 1 $fe0c pll bandwidth control register (pbwc) read: auto lock acq xld 0000 write: reset: 0 0 0 0 0 0 0 0 $fe0d pll programming register (ppg) read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 0 1 1 0 0 1 1 0 = unimplemented figure 8-2. cgm i/o register summary non-disclosure agreement required clock generator module (cgm) technical data MC68HC708MP16 ? rev. 3.1 108 clock generator module (cgm) freescale semiconductor the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and cgmxfc noise. the vco frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f vrs . modulating the voltage on the cg mxfc pin changes the frequency within this range. by design, f vrs is equal to the nom inal center-of-range frequency, f nom , (4.9152 mhz) times a li near factor l, or (l)f nom . cgmrclk is the pll reference clock, a buffered versio n of cgmxclk. cgmrclk runs at a frequency, f rclk , and is fed to t he pll through a buffer. the buffer output is the final reference cl ock, cgmrdv, running at a frequency f rdv =f rclk . the vco?s output clock, cgmvclk, running at a frequency f vclk , is fed back through a programmable modul o divider. the modulo divider reduces the vco clock by a factor, n. the dividers output is the vco feedback clock, cgmvdv, running at a frequency f vdv =f vclk /n. (see 8.4.2.4 programming the pll for more information.) the phase detector then compares th e vco feedback clock, cgmvdv, with the final reference clock, cgmrdv. a correction pulse is generated based on the phase di fference between the two si gnals. the loop filter then slightly alters t he dc voltage on the external capacitor connected to cgmxfc based on the wi dth and direction of th e correction pulse. the filter can make fa st or slow correcti ons depending on its mode, described in 8.4.2.2 acquisition and tracking modes . the value of the external capacitor and the refer ence frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the freque ncies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the speed of the lock detector is directly proportional to t he final reference frequency f rdv . the circuit determines the mode of the pll and the lock condition based on this comparison. clock generator module (cgm) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor clock generator module (cgm) 109 non-disclosure agreement required 8.4.2.2 acquisition and tracking modes the pll filter is manually or automatically conf igurable into one of two operating modes: acquisition mode ? in acquisition m ode, the filter can make large frequency corrections to the vco. th is mode is used at pll start- up or when the pll has suffered a severe noise hit and the vco frequency is far off the desired frequency. when in acquisition mode, the acq bit is clear in the pll bandwidth cont rol register. (see 8.6.2 pll bandwidth control register .) tracking mode ? in tracking mode , the filter makes only small corrections to the frequency of t he vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode wh en the vco frequency is nearly correct, such as when the pll is selected as the base clock source. (see 8.4.3 base clock se lector circuit .) the pll is automatically in tracking mode wh en not in acqui sition mode or when the acq bit is set. 8.4.2.3 manual and auto matic pll bandwidth modes the pll can change the bandwidth or oper ational mode of the loop filter manually or automatically. in automatic bandwidth control mode (auto = 1), the lock detector automatically switches between acquisition and tracking modes. automatic bandwidth c ontrol mode also is us ed to determi ne when the vco clock, cgmvclk, is safe to us e as the source for the base clock, cgmout. (see 8.6.2 pll bandwidth control register .) if pll interrupts are enabled, th e software can wait for a pll interrupt request and then check the lock bit. if interrup ts are disabled, software can poll the lock bit cont inuously (during pll start-up, usually) or at periodic intervals. in either case, when the lo ck bit is set, the vco clock is safe to use as the source for the base clock. (see 8.4.3 base clock selector circuit .) if the vco is selected as th e source for the base clock and the lock bit is clear, the pll has suffered a seve re noise hit and the software must take appropriate ac tion, depending on the application. (see 8.7 interrupts for information and precautions on using interrupts.) non-disclosure agreement required clock generator module (cgm) technical data MC68HC708MP16 ? rev. 3.1 110 clock generator module (cgm) freescale semiconductor the following conditions apply when t he pll is in automatic bandwidth control mode: the acq bit (see 8.6.2 pll bandwidth control register ) is a read-only indicator of the mode of the filter. (see 8.4.2.2 acquisition and tracking modes .) the acq bit is set when the vco fr equency is within a certain tolerance, ? trk , and is cleared when the vco frequency is out of a certain tolerance, ? unt . (see 8.10 acquisition/lock time specifications for more information.) the lock bit is a read-only indica tor of the locked state of the pll. the lock bit is set when the vco frequency is within a certain tolerance, ? lock , and is cleared when t he vco frequency is out of a certain tolerance, ? unl . (see 8.10 acquisition/lock time specifications for more information.) cpu interrupts can occur if enabl ed (pllie = 1) when the pll?s lock condition changes, toggli ng the lock bit. (see 8.6.1 pll control register .) the pll also may operate in ma nual mode (auto = 0). manual mode is used by systems that do not requi re an indicator of the lock condition for proper operation. such systems typicall y operate well below f busmax and require fast start- up. the following conditions apply when in manual mode: acq is a writable control bit that controls t he mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. before entering tracking mode (acq = 1), software must wait a given time, t acq (see 8.10 acquisition/lock time specifications ), after turning on the pll by setting pllon in the pll control regi ster (pctl). software must wait a given time, t al , after entering tracking mode before selecting the pll as th e clock source to cgmout (bcs = 1). the lock bit is disabled. cpu interrupts from the cgm are disabled. clock generator module (cgm) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor clock generator module (cgm) 111 non-disclosure agreement required 8.4.2.4 programming the pll the following procedure shows how to program the pll. note: the round function in t he following equations m eans that the real number should be round ed to the nearest integer number. 1. choose the desired bus frequency, f busdes . 2. calculate the desired vco frequ ency (four times the desired bus frequency). 3. choose a practical pll reference frequency, f rclk . 4. select a vco frequency multiplier, n. 5. calculate and verify the adequacy of the vco and bus frequencies f vclk and f bus . 6. select a vco linear range multiplier, l. where f nom = 4.9152 mhz 7. calculate and verify the ade quacy of the vco programmed center-of-range frequency f vrs . f vrs = (l)f nom 8. verify the choice of n and l by comparing f vclk to f vrs and f vclkdes . for proper operation, f vclk must be within the application?s tolerance of f vclkdes , and f vrs must be as close as possible to f vclk . f vclkdes 4f busdes = n round f vclkdes f rclk ------------ --------- - ?? ?? = f vclk nf rclk = f bus f vclk () 4 ? = l round f vclk f nom ------------ - ?? ?? = non-disclosure agreement required clock generator module (cgm) technical data MC68HC708MP16 ? rev. 3.1 112 clock generator module (cgm) freescale semiconductor note: exceeding the recommended ma ximum bus frequency or vco frequency can cr ash the mcu. 9. program the pll r egisters accordingly: a. in the upper four bi ts of the pll progra mming register (ppg), program the binary equivalent of n. b. in the lower four bits of th e pll programming register (ppg), program the binary equivalent of l. 8.4.2.5 special programming exceptions the programming method described in 8.4.2.4 programming the pll does not account for possible exceptions . a value of zero for n or l is meaningless when used in the equations given. to account for these exceptions: a zero value for n is interprete d exactly the same as a value of one. a zero value for l di sables the pll and prev ents its selection as the source for the base clock. (see 8.4.3 base clock selector circuit .) 8.4.3 base clock selector circuit this circuit is used to select either the crystal clock, cgmxclk, or the vco clock, cgmvclk, as the source of the ba se clock, cgmout. the two input clocks go thro ugh a transition control ci rcuit that waits up to three cgmxclk cycles and three cg mvclk cycles to change from one clock source to the other. duri ng this time, cgmout is held in stasis. the output of the transition co ntrol circuit is then divided by two to correct the duty cycle. therefore, the bus clo ck frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (cgmxclk or cgmvclk). the bcs bit in the pll cont rol register (pctl) sele cts which clock drives cgmout. the vco clock c annot be selected as t he base clock source if the pll is not turned on. the pll cannot be turned off if the vco clock is selected. the pll cannot be tur ned on or off simultaneously with the clock generator module (cgm) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor clock generator module (cgm) 113 non-disclosure agreement required selection or deselection of the vco clock. the vco clock also cannot be selected as the base clock source if the factor l is programmed to a zero. this value would set up a conditi on inconsistent with the operation of the pll, so that the pll would be disabled and the crystal clock would be forced as the source of the base clock. 8.4.4 cgm external connections in its typical confi guration, the cgm requ ires seven external components. five of thes e are for the crystal o scillator and two are for the pll. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 8-3 . figure 8-3 shows only the logical representation of the internal components and ma y not represent actual circuitry. the oscillator conf iguration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be r equired for all rang es of operation, especially with high frequency cryst als. refer to the crystal manufacturer?s data for more information. figure 8-3 also shows the exter nal components for the pll: bypass capacitor, c byp filter capacitor, c f routing should be done with great care to mini mize signal cross talk and noise. (see 8.10 acquisition/loc k time specifications for routing information and more info rmation on the filter capacitor?s value and its effects on pll performance.) non-disclosure agreement required clock generator module (cgm) technical data MC68HC708MP16 ? rev. 3.1 114 clock generator module (cgm) freescale semiconductor figure 8-3. cgm external connections 8.5 i/o signals the following paragraphs descr ibe the cgm i/o signals. 8.5.1 crystal amplifier input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 8.5.2 crystal amplifier output pin (osc2) the osc2 pin is the output of the crystal oscillator inverting amplifier. 8.5.3 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to fi lter out phase corrections. a small external capac itor is connected to this pin. c 1 c 2 c f simoscen cgmxclk r b x 1 r s * c byp osc1 osc2 v ss cgmxfc v dda *r s can be zero (shorted) when used with higher -frequency crystals. refer to manufacturer?s data. v dd clock generator module (cgm) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor clock generator module (cgm) 115 non-disclosure agreement required note: to prevent noise problems, c f should be placed as close to the cgmxfc pin as possible, with minimum routing distances and no routing of other si gnals across the c f connection. 8.5.4 pll analog power pin (v dda ) v dda is a power pin used by the analog portions of the p ll. connect the v dda pin to the same vo ltage potential as the v dd pin. note: route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 8.5.5 oscillator enable signal (simoscen) the simoscen signal come s from the system int egration module (sim) and enables the osci llator and pll. 8.5.6 crystal output frequency signal (cgmxclk) cgmxclk is the crystal o scillator output signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 8-3 shows only the logical relati on of cgmxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of cgmxclk is unknown and may depend on the crystal and other external factors. also, the frequen cy and amplitude of cgmxclk can be unstable at start-up. 8.5.7 cgm base clock output (cgmout) cgmout is the clock output of the cgm. this signal goes to the sim, which generates the mcu clocks. cgmout is a 50% duty cycle clock running at twice the bus frequency. cgmout is software programmable to be either the oscillator output, cgmxclk, divided by two or the vco clock, cgmvclk, divided by two. non-disclosure agreement required clock generator module (cgm) technical data MC68HC708MP16 ? rev. 3.1 116 clock generator module (cgm) freescale semiconductor 8.5.8 cgm cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector. 8.6 cgm registers the following registers control and monitor operation of the cgm: pll control regi ster (pctl) (see 8.6.1 pll control register .) pll bandwidth control register (pbwc) (see 8.6.2 pll bandwidth control register .) pll programming regi ster (ppg) ((see 8.6.3 pll programming register .) figure 8-4 is a summary of t he cgm registers. pctl $fe0bbit 7654321bit 0 read: pllie pllf pllon bcs 1111 write: pbwc $fe0cbit 7654321bit 0 read: auto lock acq xld 0000 write: ppg $fe0dbit 7654321bit 0 read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: = unimplemented notes: 1. when auto = 0, pllie is forced to logic 0 and is read-only. 2. when auto = 0, pllf and lock read as logic 0. 3. when auto = 1, acq is read-only. 4. when pllon = 0 or vrs[7:4] = $0, bcs is forced to logic 0 and is read-only. 5. when pllon = 1, the pll programming register is read-only. 6. when bcs = 1, pllon is forced set and is read-only. figure 8-4. cgm i/o register summary clock generator module (cgm) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor clock generator module (cgm) 117 non-disclosure agreement required 8.6.1 pll control register the pll control register contains t he interrupt enable a nd flag bits, the on/off switch, the base clock selector bit. pllie ? pll interrupt enable bit this read/write bi t enables the pll to gener ate an interrupt request when the lock bit toggles, sett ing the pll flag, pllf. when the auto bit in the pll bandwidth c ontrol register (pbwc) is clear, pllie cannot be written and reads as logic 0. reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf ? pll interrupt flag bit this read-only bit is set wheneve r the lock bit toggles. pllf generates an interrupt request if th e pllie bit also is set. pllf always reads as logic 0 when t he auto bit in the pll bandwidth control register (pbwc) is clear . clear the pllf bi t by reading the pll control register. re set clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note: do not inadvertently cl ear the pllf bit. any re ad or read-modify-write operation on the pll control regi ster clears the pllf bit. address: $fe0b bit 7654321bit 0 read: pillie pllf pllon bcs 1111 write: reset: 0 0 10 1111 = unimplemented figure 8-5. pll cont rol register (pctl) non-disclosure agreement required clock generator module (cgm) technical data MC68HC708MP16 ? rev. 3.1 118 clock generator module (cgm) freescale semiconductor pllon ? pll on bit this read/write bit activates t he pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving the base clock, cgmout (bcs = 1). (see 8.4.3 base clock selector circuit .) reset sets this bit so that the loop can stabi lize as the mcu is powering up. 1 = pll on 0 = pll off bcs ? base clock select bit this read/write bit sele cts either the crystal oscillator output, cgmxclk, or the vco clock, cgm vclk, as the sour ce of the cgm output, cgmout. cgmout frequency is one-ha lf the frequency of the selected clock. bcs cannot be set while t he pllon bit is clear. after toggling b cs, it may take up to three cgmxclk and three cgmvclk cycles to complete the tr ansition from one source clock to the other. during the transition, cgmout is held in stasis. (see 8.4.3 base clock sel ector circuit .) reset clears the bcs bit. 1 = cgmvclk divided by two drives cgmout. 0 = cgmxclk divided by two drives cgmout. note: pllon and bcs have built-in protec tion that prevents the base clock selector circuit from se lecting the vco clock as the source of the base clock if the pll is of f. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is clear. if the pll is off (pllon = 0), selecting cgmvclk require s two writes to the pll control register. (see 8.4.3 base clock se lector circuit .) pctl[3:0] ? unimplemented bits these bits provide no function and always read as logic 1s. clock generator module (cgm) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor clock generator module (cgm) 119 non-disclosure agreement required 8.6.2 pll bandwidth control register the pll bandwidth control regi ster does the following: selects automatic or manual (software-controlled) bandwidth control mode indicates when the pll is locked in automatic bandwidth control mode , indicates when the pll is in acquisition or tracking mode in manual operation, forces the pll into acquisition or tracking mode. auto ? automatic bandwidth control bit this read/write bit sele cts automatic or manual bandwidth control. when initializing the p ll for manual operation (auto = 0), clear the acq bit before turning on the pll. reset cl ears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ? lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock, cgmvclk, is lo cked (running at the programmed frequency). when the auto bit is clear, lock reads as logic 0 and has no meaning. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency inco rrect or unlocked address: $fe0c bit 7654321bit 0 read: auto lock acq xld 0000 write: reset: 0 0 00 0000 = unimplemented figure 8-6. pll bandwidth control register (pbwc) non-disclosure agreement required clock generator module (cgm) technical data MC68HC708MP16 ? rev. 3.1 120 clock generator module (cgm) freescale semiconductor acq ? acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tr acking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisiti on or tracking mode. in automatic bandwidth control mode (auto = 1), the last-written value from manual operati on is stored in a te mporary location and is recovered when manual oper ation resumes. rese t clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode xld ? crystal loss detect bit when the vco output, cgmvclk, is driving cgmout, this read/write bit can in dicate whether the crystal reference frequency is active or not. to check the status of the crystal reference, do the following: 1. write a logic 1 to xld. 2. wait n 4 cycles. (n is the vc o frequency multiplier.) 3. read xld. 1 = crystal refere nce is not active 0 = crystal reference is active the crystal loss detect function wor ks only when the bcs bit is set, selecting cgmvclk to drive cg mout. when bcs is clear, xld always reads as logic 0. pbwc[3:0] ? reserved for test these bits enable test functions not available in user mode. to ensure software portability fr om development systems to user applications, software should write zeros to pbw c[3:0] whenever wr iting to pbwc. clock generator module (cgm) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor clock generator module (cgm) 121 non-disclosure agreement required 8.6.3 pll programming register the pll programming regist er contains the program ming information for the modulo feedback divider and the programming information for the hardware configurat ion of the vco. mul[7:4] ? multip lier select bits these read/write bits control the m odulo feedback divider that selects the vco frequency multiplier, n. (see 8.4.2.1 pll circuits and 8.4.2.4 programming the pll .) a value of $0 in th e multiplier select bits configures the m odulo feedback divider th e same as a value of $1. reset initializes these bits to $6 to give a defaul t multiply value of 6. address: $fe0d bit 7654321bit 0 read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 figure 8-7. pll programming register (ppg) non-disclosure agreement required clock generator module (cgm) technical data MC68HC708MP16 ? rev. 3.1 122 clock generator module (cgm) freescale semiconductor note: the multiplier select bits have built-in protection that prevents them from being written when the p ll is on (pllon = 1). vrs[7:4] ? vco r ange select bits these read/write bits control the hardware center-of-range linear multiplier l, which controls the hardware cent er-of-range frequency f vrs . (see 8.4.2.1 pll circuits , 8.4.2.4 programming the pll , and 8.6.1 pll control register .) vrs[7:4] cannot be written when the pllon bit in the pll control register (pctl) is set. (see 8.4.2.5 special programming exceptions .) a value of $0 in the vco range select bits disables the pll and clears the bc s bit in the pctl. (see 8.4.3 base clock selector circuit and 8.4.2.5 special programming exceptions for more informatio n.) reset initializes the bits to $6 to gi ve a default range mu ltiply value of 6. note: the vco range select bits have built-i n protection that prevents them from being written when the pll is on (p llon = 1) and prevents selection of the vco clo ck as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the vco range select bits must be programmed correctly. incorrect programming may result in failur e of the pll to achieve lock. table 8-1. vco frequency mu ltiplier (n) selection mul7:mul6:mul5:mul4 vco frequency multiplier (n) 0000 1 0001 1 0010 2 0011 3 1101 13 1110 14 1111 15 clock generator module (cgm) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor clock generator module (cgm) 123 non-disclosure agreement required 8.7 interrupts when the auto bit is set in the pll bandwidth control register (pbwc), the pll can generate a cpu interrupt request ev ery time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts ar e enabled or not. when the auto bit is clear, cpu interrupts from the p ll are disabled and pllf reads as logic 0. software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit fr om lock. when the pll enters lock, the vco clock, cgmvclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock fr equency is corrupt, and appropriate precautions should be taken. if the application is not frequency- sensitive, interrupts s hould be disabled to prevent pll interrupt service routines from impedi ng software performance or from exceeding stack limitations. note: software can select the cgmvclk divided by two as the cgmout source even if the p ll is not locked (lock = 0). therefore, software should make sure the pll is lo cked before setting the bcs bit. 8.8 wait mode the wait instruction puts the mcu in low-power-consumption standby mode. the wait instruction does not affect the cgm. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control r egister (pctl). less power-sensitive applications can disengage the pll without turning it off. applications that require the pll to wake the mcu from wait mode also can deselect the pll output without turning off the pll. non-disclosure agreement required clock generator module (cgm) technical data MC68HC708MP16 ? rev. 3.1 124 clock generator module (cgm) freescale semiconductor 8.9 cgm during break mode the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during t he break state. (see 7.7.4 sim break flag control register .) to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect the pllf bit dur ing the break state, writ e a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), software can read and write the pll control register during the break state without affecting the pllf bit. 8.10 acquisition/lock time specifications the acquisition and lo ck times of the pll are, in many applications, the most critical pll desi gn parameters. proper desig n and use of the pll ensures the highest stability and lowest acquisi tion/lock times. 8.10.1 acquisition/lock time definitions typical control systems refer to the ac quisition time or lock time as the reaction time, within specified tolera nces, of the system to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually specified as a percent of the step input or when the ou tput settles to the desi red value plus or minus a percent of the frequen cy change. therefore, t he reaction time is constant in this definit ion, regardless of the si ze of the step input. for example, consider a system with a 5% acquisition time tolerance. if a command instructs the system to change from 0 hz to 1 mhz, the acquisition time is the time ta ken for the frequency to reach 1mhz 50 khz. fifty khz = 5% of the 1-mh z step input. if the system is operating at 1 mhz and suff ers a ?100-khz noise hit, the acquisition time clock generator module (cgm) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor clock generator module (cgm) 125 non-disclosure agreement required is the time taken to re turn from 900 khz to 1 mhz 5 khz. five khz = 5% of the 100-khz step input. other systems refer to ac quisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified toleranc es. therefore, the acquisition or lock time varies according to the original error in the output . minor errors may not even be registered. typical pll applications prefer to use this definition because the system requires the out put frequency to be within a certain tolerance of the desired fr equency regardless of the size of the initial error. the discrepancy in these definitions ma kes it difficult to specify an acquisition or lock time for a typical pll. therefor e, the definitions for acquisition and lock times for th is module are as follows: acquisition time, t acq , is the time the pll ta kes to reduce the error between the actual output fr equency and the desired output frequency to less than the tra cking mode entry tolerance, ? trk . acquisition time is based on an initial frequency error, (f des ? f orig )/f des , of not more than 100%. in automatic bandwidth control mode (see 8.4.2.3 manual and automatic pll bandwidth modes ), acquisition time expires when the acq bit becomes set in the pll bandwid th control regi ster (pbwc). lock time, t lock , is the time the pll ta kes to reduce the error between the actual output fr equency and the desired output frequency to less than the lock mode entry tolerance, ? lock . lock time is based on an init ial frequency error, (f des ? f orig )/f des , of not more than 100%. in automatic bandwidth control mode, lock time expires when the lock bit becomes se t in the pll bandwidth control regi ster (pbwc). (see 8.4.2.3 manual and automatic pll bandwidth modes .) obviously, the acquisition and lock ti mes can vary according to how large the frequency error is and may be shorter or longer in many cases. non-disclosure agreement required clock generator module (cgm) technical data MC68HC708MP16 ? rev. 3.1 126 clock generator module (cgm) freescale semiconductor 8.10.2 parametric influences on reaction time acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. these reaction times are not constant, however. many factors di rectly and indirect ly affect the acquisition time. the most critical parameter which af fects the reaction times of the pll is the reference frequency, f rdv . this frequency is the input to the phase detector and controls how often the pll makes corr ections. for stability, the corrections must be small compared to t he desired frequency, so several corrections are requir ed to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is also un der user control via the choice of crystal frequency, f xclk . another critical parameter is the external filter capacitor. the pll modifies the voltage on the vco by adding or subtracting charge from this capacitor. therefore, the rate at which t he voltage changes for a given frequency error (thus change in charge) is propo rtional to the capacitor size. the si ze of the capa citor also is related to the stability of the pll. if the capacitor is too small, the pl l cannot make small enough adjustments to the volt age and the system cannot lo ck. if the capacitor is too large, the pl l may not be able to ad just the voltage in a reasonable time. (see 8.10.3 choosing a filter capacitor .) also important is th e operating voltage po tential applied to v dda . the power supply potential alters the charac teristics of the p ll. a fixed value is best. variable supplies, such as bat teries, are acceptable if they vary within a known range at very slow speeds. noise on the power supply is not acceptable, because it caus es small frequency errors which continually change the acquisi tion time of the pll. temperature and processing also can af fect acquisition time because the electrical characteristics of the pll change. the part operates as specified as long as these influences stay within the specified limits. external factors, however, can caus e drastic changes in the operation of the pll. these factors include noise injected into t he pll through the filter capacitor, filter capacitor leakage, stray impedanc es on the circuit board, and even hum idity or circuit board contamination. clock generator module (cgm) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor clock generator module (cgm) 127 non-disclosure agreement required 8.10.3 choosing a filter capacitor as described in 8.10.2 parametric infl uences on r eaction time , the external filter capacitor, c f , is critical to the stability and reaction time of the pll. the pll is also dependent on reference frequency and supply voltage. the value of t he capacitor must, ther efore, be chosen with supply potential and reference fre quency in mind. for proper operation, the external filter capac itor must be chosen a ccording to the following equation: for acceptable values of c fact , see table 21-10. cgm acquisition/lock ti me specifications . for the value of v dda , choose the voltage potential at wh ich the mcu is operati ng. if the power supply is variable, choose a value near t he middle of the range of possible supply values. this equation does not always yield a commonl y available capacitor size, so round to t he nearest available size. if the value is between two different sizes, choose the higher va lue for better stability. choosing the lower size may seem attractive for acquisition time impr ovement, but the pll can become unstable. also, alwa ys choose a capacitor with a tight tolerance ( 20% or better) and low dissipation. 8.10.4 reaction time calculation the actual acquisition and lock time s can be calculated using the equations below. these equations yield nominal values under the following conditions: correct selection of filter capacitor, c f (see 8.10.3 choosing a filter capacitor .) room temperature operation negligible external leakage on cgmxfc negligible noise c f c fact v dda f rdv ------------ - ?? ?? = non-disclosure agreement required clock generator module (cgm) technical data MC68HC708MP16 ? rev. 3.1 128 clock generator module (cgm) freescale semiconductor the k factor in the equatio ns is derived from in ternal pll parameters. k acq is the k factor when the pll is configured in acquisition mode, and k trk is the k factor when the pll is configured in tra cking mode. (see 8.4.2.2 acquisiti on and tracking modes .) note the inverse proportionality bet ween the lock time and the reference frequency. in automatic bandwidth control m ode, the acquisition and lock times are quantized into units based on th e reference frequency. (see 8.4.2.3 manual and automatic pll bandwidth modes .) a certain number of clock cycles, n acq , is required to ascertain th at the pll is within the tracking mode entry tolerance, ? trk , before exiting acquisition mode. a certain number of clock cycles, n trk , is required to a scertain that the pll is within the lock mode entry tolerance, ? lock . therefore, the acquisition time, t acq , is an integer multiple of n acq /f rdv , and the acquisition to lock time, t al , is an integer multiple of n trk /f rdv . also, since the average frequency over t he entire measurem ent period must be within the specified tole rance, the total time usually is longer than t lock as calculated above. in manual mode, it is us ually necessary to wait considerably longer than t lock before selecting t he pll clock (see 8.4.3 base clock selector circuit ) because the factors described in 8.10.2 parametric influences on reaction time may slow the lock time considerably. t acq v dda f rdv ----------- - ?? ?? 8 k acq ----------- - ?? ?? = t al v dda f rdv ----------- - ?? ?? 4 k trk ----------- ?? ?? = t lock t acq t al + = MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 129 non-disclosure agreement required technical data ? MC68HC708MP16 section 9. pulse width modulator for motor control (pwmmc) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.4 timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.4.1 resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.4.2 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.5 pwm generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.5.1 load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.5.2 pwm data overflow and underf low conditions . . . . . . . . 142 9.6 output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.6.1 selecting six independent pwms or three complementary pwm pair s . . . . . . . . . . . . . 142 9.6.2 dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 9.6.3 top/bottom correction . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9.6.3.1 manual correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.6.3.2 automatic correction . . . . . . . . . . . . . . . . . . . . . . . . . . .154 9.6.4 output polarity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 9.6.5 output port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 9.7 fault protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 9.7.1 fault condition input pi ns . . . . . . . . . . . . . . . . . . . . . . . . . 164 9.7.1.1 fault pin filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 9.7.1.2 automatic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 9.7.1.3 manual mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 9.7.2 software output disabl e . . . . . . . . . . . . . . . . . . . . . . . . . . 168 9.7.3 output port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 9.8 initialization and the pwm en bit . . . . . . . . . . . . . . . . . . . . . . 169 9.9 pwm operation in wait mode . . . . . . . . . . . . . . . . . . . . . . . . 171 9.10 pwm operation in break mode . . . . . . . . . . . . . . . . . . . . . . .171 non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 130 pulse width modulator for motor control (pwmmc) freescale semiconductor 9.11 control logic block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 9.11.1 pwm counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . 172 9.11.2 pwm counter modulo registers. . . . . . . . . . . . . . . . . . . .173 9.11.3 pwm x value registers . . . . . . . . . . . . . . . . . . . . . . . . . . 174 9.11.4 pwm control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 175 9.11.5 pwm control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 177 9.11.6 dead-time write-once register . . . . . . . . . . . . . . . . . . . .179 9.11.7 pwm disable mapping write-once register . . . . . . . . . . 180 9.11.8 fault control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 9.11.9 fault status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 9.11.10 fault acknowledge regist er . . . . . . . . . . . . . . . . . . . . . . .185 9.11.11 pwm output control r egister. . . . . . . . . . . . . . . . . . . . . . 186 9.12 pwm glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 9.2 introduction this section describes the pulse width modulator for motor control (pwmmc, version a). the mc68h c(7)08mp16 pwm module can generate three complementary pw m pairs or six independent pwm signals. these pwm si gnals can be center-aligned or edge-aligned. a block diagram of the pw m module is shown in figure 9-1 . a12-bit timer pwm counter is co mmon to all six channels. pwm resolution is one clock period fo r edge-aligned operation and two clock periods for center-aligned operation. the clock peri od is dependent on the internal oper ating frequency (f op ) and a programmable prescaler. the highest resolution for edge-al igned operation is 125 ns (f op = 8 mhz). the highest resolution for ce nter-aligned operati on is 250 ns (f op = 8 mhz). when generating complementary pwm signals, the m odule features automatic dead-time insertion to t he pwm output pairs and transparent toggling of pwm data bas ed upon sensed motor phase current polarity. a summary of the pwm r egisters is shown in figure 9-2 . pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 131 non-disclosure agreement required 9.3 features features of the pwmmc include the following: three complimentary pwm pairs or six independent pwm signals edge-aligned pwm signals or center-a ligned pwm signals pwm signal polarity control 20 ma current sink capability on pwm pins manual pwm output cont rol through software programmable fault protection complimentary m ode also features: ? dead-time insertion ? separate top/bottom pulse width correction via current sensing or programmable software bits figure 9-1. pwm module block diagram pwm1pin pwm2pin pwm channels 3 & 4 pwm3pin pwm4pin pwm channels 5 & 6 pwm5pin pwm6pin timebase cpu bus output control coil current polarity pins 3 4 fault interrupt pins 12 control logic block 8 pwm channels 1 & 2 fault protection non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 132 pulse width modulator for motor control (pwmmc) freescale semiconductor addr. name bit 7 6 5 4 3 2 1 bit 0 $0020 pwm control register 1 (pctl1) read: disx disy pwmint pwmf isens1 isens0 ldok pwmen write: reset: 0 0 0 0 0 0 0 0 $0021 pwm control register 2 (pctl2) read: ldfq1 ldfq0 0 ipol1 ipol2 ipol3 prsc1 prsc0 write: reset: 0 0 0 0 0 0 0 0 $0022 fault control register (fcr) read: fint4 fmode4 fint3 fmode3 fint2 fmode2 fint1 fmode1 write: reset: 0 0 0 0 0 0 0 0 $0023 fault status register (fsr) read: fpin4 fflag4 fpin3 ffla g3 fpin2 fflag2 fpin1 fflag1 write: reset: u 0 u 0 u 0 u 0 $0024 fault acknowledge register (ftack) read: 0 0 0 0 0 0 0 0 write: ftack4 ftack3 ftack2 ftack1 reset: 0 0 0 0 0 0 0 0 $0025 pwm output control (pwmout) read: 0 outctl out6 out5 out4 out3 out2 out1 write: reset: 0 0 0 0 0 0 0 0 $0026 pwm counter register high (pcnth) read: 0 0 0 0 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0027 pwm counter register low (pcntl) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0028 pwm counter modulo register high (pmodh) read: 0 0 0 0 11 10 9 bit 8 write: reset: 0 0 0 0 x x x x x = indeterminate u = unaffected = unimplemented figure 9-2. pwmmc register summary pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 133 non-disclosure agreement required $0029 pwm counter modulo register low (pmodl) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: x x x x x x x x $002a pwm 1 value register high (pval1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002b pwm 1 value register low (pval1l) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $002c pwm 2 value register high (pval2h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002d pwm 2 value register low (pval2l) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $002e pwm 3 value register high (pval3h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002f pwm 3 value register low (pval3l) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0030 pwm 4 value register high (pval4h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0031 pwm 4 value register low (pval4l) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 addr. name bit 7 6 5 4 3 2 1 bit 0 x = indeterminate u = unaffected = unimplemented figure 9-2. pwmmc register summary non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 134 pulse width modulator for motor control (pwmmc) freescale semiconductor $0032 pwm 5 value register high (pval5h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0033 pwm 5 value register low (pval5l) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0034 pwm 6 value register high (pval6h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0035 pwm 6 value register low (pval6l) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0036 dead timer write-once register (deadtm) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0037 pwm disable mapping write- once register (dismap) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 addr. name bit 7 6 5 4 3 2 1 bit 0 x = indeterminate u = unaffected = unimplemented figure 9-2. pwmmc register summary pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 135 non-disclosure agreement required 9.4 timebase refer to the following subsection s for a discussion of the timebase. 9.4.1 resolution in center-aligned mode, a 12-bit up/down counter is used to create the pwm period. therefore, the pwm resolution in center-aligned mode is two clocks (highest reso lution is 250 ns @ f op = 8 mhz) as shown in figure 9-3 . the up/down counter uses the value in the timer modulus register to det ermine its maximum count. the pwm period will equal: [(timer modulus) x (pwm clock period) x 2]. figure 9-3. center-aligned pwm (positive polarity) up/down counter modulus = 4 pwm = 0 pwm = 1 pwm = 2 pwm = 3 pwm = 4 period = 8 x (pwm clock period) non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 136 pulse width modulator for motor control (pwmmc) freescale semiconductor for edge-aligned m ode, a 12-bit up-only counter is used to create the pwm period. therefore, the pwm re solution in edge- aligned mode is one clock (highest resolution is125 ns @ f op = 8 mhz) as shown in figure 9-4 . again, the timer modulus regi ster is used to determine the maximum count. the pwm period will equal: [(timer modulus) x (pwm clock period)]. center-aligned operation versus edge-aligned operation is determined by the option edge. see 5.3 functional description . figure 9-4. edge-aligned pwm (positive polarity) up-only counter modulus = 4 pwm = 0 pwm = 1 pwm = 2 pwm = 3 pwm = 4 period = 4 x (pwm clock period) pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 137 non-disclosure agreement required 9.4.2 prescaler to permit lower pwm freque ncies, a prescaler is provided which will divide the pwm clock frequen cy by 1, 2, 4, or 8. table 9-1 shows how setting the prescaler bits in pwm control register 2 affects the pwm clock frequency. this prescaler is bu ffered and will not be used by the pwm generator until the ldok bit is set and a new pwm reload-cycle begins. 9.5 pwm generators pulse width modulator (p wm) generators are discu ssed in the following subsections. 9.5.1 load operation to help avoid erroneous pulse widths and pwm periods, the modulus, prescaler, and pwm value register s are buffered. new pwm values, counter modulus values, and prescalers can be loaded from their buffers into the pwm module every one, tw o, four, or ei ght pwm cycles. ldfq1:ldfq0 in pwm control register 2 are used to control this reload frequency, as shown in table 9-2 . when a reload cycle arrives, regardless of whether an actual reload occurs (as determined by the ldok bit), the pwm reload flag bit in pwm control register 1 will be set. if the pwmint bit in pwm control r egister 1 is set, a cpu interrupt request will be gene rated when pwmf is set. software can use this interrupt to calculate new pwm param eters in real ti me for the pwm module. table 9-1. pwm prescaler prescaler bits prsc1:prsc0 pwm clock frequency 00 f op 01 f op /2 10 f op /4 11 f op /8 non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 138 pulse width modulator for motor control (pwmmc) freescale semiconductor for ease of software, the ldfqx bits are buffered. when the ldfqx bits are changed, the rel oad frequency will not c hange until the previous reload cycle is co mpleted. see figure 9-5 . note: when reading the ldfqx bits, the value is the buffered value (for example, not necessarily the value being acted upon). figure 9-5. rel oad frequency change pwmint enables cpu interrupt requests as shown in figure 9-6 . when this bit is set, cpu interrupt r equests are generated when the pwmf bit is set. when the pwmint bit is clear, pwm interrup t requests are inhibited. pwm reloads will still occu r at the reload rate , but no interrupt requests will be generated. table 9-2. pwm reload frequency reload frequency bits ldfq1:ldfq0 pwm reload frequency 00 every pwm cycle 01 every 2 pwm cycles 10 every 4 pwm cycles 11 every 8 pwm cycles reload reload reload reload reload reload reload change reload frequency to every 4 cycles change reload frequency to every cycle pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 139 non-disclosure agreement required figure 9-6. pwm interrupt requests to prevent a partial rel oad of pwm parameters fr om occurring while the software is still calculating them, an interlock bit contro lled from software is provided. this bit informs t he pwm module that all the pwm parameters have been calc ulated, and it is ?okay? to use them. a new modulus, prescaler, and/or pwm va lue cannot be loaded into the pwm module until the ldok bi t in pwm control regist er 1 is set. when the ldok bit is set, these new values are loaded into a second set of registers and used by t he pwm generator at the beginning of the next pwm reload cycle as shown in figure 9-7 , figure 9-8 , figure 9-9 , and figure 9-10 . after these values are l oaded, the ldok bit is cleared. note: when the pwm module is en abled (via the pwmen bit), a load will occur if the ldok bit is set. even if it is not set, an in terrupt will occur if the pwmint bit is set. to prevent this, the soft ware should clear the pwmint bit before enab ling the pwm module. latch v dd cpu interrupt reset d ck pwmint pwmf pwm reload read pwmf as 1, write pwmf as 0 or reset request non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 140 pulse width modulator for motor control (pwmmc) freescale semiconductor figure 9-7. center-ali gned pwm value loading figure 9-8. center-a ligned loading of modulus ldok = 1 modulus = 3 pwm value= 1 ldok = 1 modulus = 3 pwm value= 2 up/down counter pwm ldfq1:ldfq0 = 00 (reload every cycle) ldok = 0 modulus = 3 pwm value= 2 ldok = 0 modulus = 3 pwm value= 1 pwmf set pwmf set pwmf set pwmf set ldok = 1 pwm value = 1 modulus = 2 ldok = 1 pwm value= 1 modulus = 3 ldok = 1 pwmvalue= 1 modulus = 2 ldok = 1 pwm value= 1 modulus = 1 ldok = 0 pwm value= 1 modulus = 2 up/down counter pwm ldfq1:ldfq0 = 00 (reload every cycle) pwmf set pwmf set pwmf set pwmf set pwmf set pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 141 non-disclosure agreement required figure 9-9. edge-al igned pwm value loading figure 9-10. edge-al igned modulus loading ldok = 1 modulus = 3 pwm value= 1. ldok = 1 modulus = 3 pwm value = 2 up-only counter pwm ldfq1:ldfq0 = 00 (reload every cycle) ldok = 0 modulus = 3 pwm value= 2. ldok = 0 modulus = 3 pwm value = 1 ldok = 0 modulus = 3 pwm value = 1 pwmf set pwmf set pwmf set pwmf set pwmf set ldok = 1 modulus = 3 pwm value= 2 ldok = 1 modulus = 4 pwm value = 2 ldok = 1 modulus = 2 pwm value = 2 up-only counter pwm ldfq1:ldfq0 = 00 (reload every cycle) ldok = 0 modulus = 1 pwm value= 2 pwmf set pwmf set pwmf set pwmf set non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 142 pulse width modulator for motor control (pwmmc) freescale semiconductor 9.5.2 pwm data overflow and underflow conditions the pwm value regist ers are 16-bit registers. although the counter is only 12 bits, the user ma y write a 16-bit signed value to a pwm value register. as shown in figure 9-3 and figure 9-4 , if the pwm value is less than or equal to ze ro, the pwm will be inacti ve for the ent ire period. conversely, if the pwm value is greater than or equal to the timer modulus, the pwm will be active fo r the entire period. refer to table 9-3 . note: the terms ?active? and ?inactive? refer to the asserted and negated states of the pwm signals and sh ould not be confused with the high impedance state of the pwm pins. 9.6 output control the following subsections discuss output control. 9.6.1 selecting six independent pwms or three complementary pwm pairs the pwm outputs can be configured as six independent pwm channels or three complementary channel pairs. the option indep determines which mode is used (see 5.3 functional description ). if complementary operation is chosen, the pwm pins are paired as shown in figure 9-11 . operation of one pair is then determined by one pwm value register. this type of operation is meant for use in motor drive circuits such as the one in figure 9-12 . table 9-3. pwm data overfl ow and underflow conditions pwmvalxh:pwmvalxl cond ition pwm value used $0000 ? $0fff normal (per registers contents) $1000 ? $7fff overflow $fff $8000 ? $ffff underflow $000 pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 143 non-disclosure agreement required figure 9-11. complementary pairing figure 9-12. typi cal ac motor drive pwm value reg. pwms 1 & 2 pwms 3 & 4 pwms 5 & 6 output control pwm value reg. pwm value reg. pwm1 pin pwm2 pin pwm3 pin pwm4 pin pwm5 pin pwm6 pin (polarity & dead-time insertion) pwm 1 pwm 2 pwm 3 pwm 4 pwm 5 pwm 6 ac to motor inputs non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 144 pulse width modulator for motor control (pwmmc) freescale semiconductor when complementary operation is us ed, two additiona l features are provided: dead-time insertion separate top/bottom pulse widt h correction to correct for distortions caused by the mo tor drive characteristics. if independent operation is chosen, each pwm has it s own pwm value register. 9.6.2 dead-time insertion as shown in figure 9-12 , in complementary mo de, each pwm pair can be used to drive top-side/b ottom-side transistors. when controlling dc-to-ac inverters su ch as this, the top and bottom pwms in one pair should never be active at the same time. in figure 9- 12 , if pwm1 and pwm2 were on at th e same time, lar ge currents would flow through the two transistors as they discharge the bus capacitor. the igbts could be we akened or destroyed. simply forcing the two pwms to be in versions of each other is not always sufficient. since a time delay is associated with tu rning off the transistors in the motor drive, ther e must be a ?dead-time? between the deactivation of one pwm and the ac tivation of the other. a dead-time can be specified in the dead-time write-once register. this 8-bit value specifies the number of cpu clock cycles to use for the dead- time. the dead-time is not affected by changes in the pwm period caused by the prescaler. dead-time insertion is achieved by feeding the top pw m outputs of the pwm generator into dead-time generators, as shown in figure 9-13 . current sensing determines which pw m value of a pwm generator pair to use for the top pwm in the next pwm cycle. (see 9.6.3 top/bottom correction .) when output control is enabled, the odd out bits, rather than the pwm generator out puts, are fed into t he dead-time generators. (see 9.6.5 output port control . ) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width modulator for motor control (pwmmc) 145 pulse width modulator for motor control (pwmmc) non-disclosure agreement required figure 9-13. dead-time generators fault polarity/output drive pwmgen<1:6> pwmpair12 pwmpair34 pwmpair56 mux pwm(top) outx select predt(top) dead timer top/bottom generation postdt (top) top/bottom generation top/bottom generation top bottom top bottom top bottom pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 6 mux pwm (top) outx select predt (top) mux pwm (top) outx select predt (top) mux pwm (top) outx select predt (top) dead-time dead timer postdt (top) dead-time dead timer postdt (top) dead-time (top) (top) (top) (pwm1) (pwm2) (pwm3) (pwm4) (pwm5) (pwm6) output control out1 out3 out5 outctl out2 out4 out6 (outctl) current sensing pwm generator non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 146 pulse width modulator for motor control (pwmmc) freescale semiconductor whenever an input to a dead-time generator transitions, a dead-time is inserted (for example, both pwms in the pair are forced to their inactive state). the bottom pw m signal is generated fr om the top pwm and the dead-time. in the case of output control enabled, the odd outx bits control the top pwms, the even outx bits control the bottom pwms with respect to t he odd outx bits . (see table 9-7 .) figure 9-14 shows the effects of the dead -time insertion. as seen in figure 9-14 , some pulse width dist ortion occurs when the dead-time is inserted. the active pulse widths are reduced. for example, in figure 9-14 , when the pwm value regi ster is equal to two, the ideal waveform (with no dead-time) has pul se widths equal to four. however, the actual pulse widths shrink to two after a dead-time of two was inserted. in this example, with the prescaler set to divide by one and center-aligned operation selected, th is distortion can be compensated for by adding or s ubtracting half the dead-time value to or from the pwm register value. this correcti on is further described in 9.6.3 top/bottom correction . further examples of dead-tim e insertion are shown in figure 9-15 and figure 9-16 . figure 9-15 shows the effects of de ad-time insertion at the duty cycle boundaries (near 0% and 100% duty cycles). figure 9-16 shows the effects of dead- time insertion on pulse widths smaller than the dead-time. pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 147 non-disclosure agreement required figure 9-14. effects of dead-time insertion figure 9-15. dead- time at duty cycle boundaries pwm value = 2 pwm value = 2 pwm value = 3 pwm1 w/ pwm2 w/ pwm1 w/ pwm2 w/ no dead-time no dead-time dead-time=2 dead-time=2 2 2 2 2 up/down counter modulus = 4 2 2 up/down counter modulus = 3 pwm value = 1 pwm value = 3 pwm value = 3 pwm1 w/ no dead-time pwm2 w/ no dead-time pwm1 w/ dead-time = 2 pwm2 w/ dead-time = 2 2 2 2 2 pwm value = 1 non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 148 pulse width modulator for motor control (pwmmc) freescale semiconductor figure 9-16. dead-time and small pulse widths 3 3 3 3 3 3 up/down counter moudulus = 3 pwm value = 2 pwm value = 3 pwm value = 2 pwm value= 1 pwm1 w/ no dead time pwm2 w/ no dead time pwm1 w/ dead time = 3 pwm2 w/ dead time = 3 pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 149 non-disclosure agreement required 9.6.3 top/bottom correction in a half-bridge ac motor drive, eit her the top or t he bottom transistor controls the output voltage at any gi ven time. the direct ion of the motor current determines which tran sistor controls the output. figure 9-17. current convention during deadtime, both transistors in a half-bridge ar e off, allowing the load voltage to float and introducin g distortion in th e output voltage. figure 9-18. d eadtime distortion positive current negative current desired deadtime pwm to top positive negative pwm to bottom positive current negative current load voltage transistor transistor load voltage load voltage current current non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 150 pulse width modulator for motor control (pwmmc) freescale semiconductor during deadtime, load inductance di storts output voltage by keeping inductive current flowing through the diodes. inductive distortion either lengthens or shortens the pulse width by one deadtime interval, depending on current direction. this deadtime distorti on then either increases or decreases the aver aged sinusoidal output voltage. figure 9-19. sinusoidal di stortion of load voltage in complementary chann el operation, either the odd-numbered or the even-numbered pwmval registers con trol the pulse width at any given time. for a given pwm pair, whether the odd or even pw mval registers are active depends on either: the state of the current-sensing pin, isx, for that driver, or the state of the output polarity bit, ipolx, fo r that driver negative current positive current desired voltage pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 151 non-disclosure agreement required to correct deadtime distortion, soft ware can decrease or increase the value in the appropriate pwmval register. in edge-aligned oper ation, decreasing or increasing the pwm value by a correction value equal to the deadtime compensates for deadtime distortion. in center aligned operation, decreasing or increasing the pwm value by a correction value equal to one-half the deadtime compensates for deadtime distortion. in complementary channel operation, the isens1?3 bits in pwm control register 1 select one of three correction methods: manual correction automatic current-sensin g correction during deadtime automatic current sensing co rrection when the pwm counter value equals the value in the pwm counter modulus registers. note: the isensx bits ar e not buffered; therefor e, changing the current sensing method can affect the present pwm cycle. table 9-4. correcti on method selection isens[1:0] correction method 0x manual correction with ipol1?ipol3 bits; or for no correction 10 automatic current-sensing correction on pins is1 , is2 , and is3 during deadtime (1) 1. the polarity of the isx pin is latched when both the top and bottom pwms are off. at the 0% and 100% duty cycle boundaries, there is no deadtime, so no new current value is sensed. 11 automatic current-sensing correction on pins is1 , is2 , and is3 (2) at the half cycle in center-aligned operation at the end of the cycle in edge-aligned operation 2. current is sensed even with 0% or 100% duty cycle. non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 152 pulse width modulator for motor control (pwmmc) freescale semiconductor 9.6.3.1 manual correction the ipol1?ipol3 bits se lect either th e odd or the even pwm value registers to use in the next pwm cycle. note: the ipolx bits are buffered so that only one pwm register is used per pwm cycle. if an ipolx bit changes during a pwm period, the new value does not take effect unt il the next pwm period. the ipolx bits take effect at the end of each pwm cycle regardless of the state of the load okay bit, ldok. figure 9-20. internal correct ion logic when isens[1:0] = 0x the best time to change from one pwmv al register to another is just before the current zero crossing. figure 9-21 shows motor voltage waveforms under high current and lo w current conditions. during a table 9-5. top/bottom manual correction bit logic state output control ipol1 0 pmval1 controls pwm1/pwm2 pair 1 pmval2 controls pwm1/pwm2 pair ipol2 0 pmval3 controls pwm3/pwm4 pair 1 pmval4 controls pwm3/pwm4 pair ipol3 0 pmval5 controls pwm5/pwm6 pair 1 pmval6 controls pwm5/pwm6 pair pwm controlled by pwm controlled by deadtime generator dq clk ipolx bit a /b a b top pwm bottom pwm odd pwmval register even pwmval register pwm cycle start pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 153 non-disclosure agreement required deadtime interval, the load voltage near a current zero crossing is somewhere between the high and low levels. figure 9-21. output voltage waveforms each isx pin is sampled twice in a pwm period. the values are stored in the dtx bits in the fault acknowle ge register. the dtx bits are a timing marker to indicate when to toggle between pwmval register. in the low- current condition immedi ately before a current ze ro crossing, the two dtx bits in a pair have dissimilar values. software can then set the ipolx bit to toggle pwmval regist ers before the zero crossing ocurs. deadtime pwm to top positive negative pwm to bottom load voltage with load voltage with transistor transistor high positive current low positive current current current load voltage with high negative current load voltage with low negative current tbtb t = deadtime interval before assertion of top pwm b = deadtime interval before assertion of bottom pwm non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 154 pulse width modulator for motor control (pwmmc) freescale semiconductor figure 9-22. dtx bits 9.6.3.2 automatic correction the current sense pin, isx , for a pwm pair selects either the odd or the even pwm value registers to use in the next pwm cycle. the selection is based on user-provided current sense circuitry driving the isx pin high for negative current and lo w for positive current. positive negative current current pwm1 pwm2 dq clk dq clk voltage sensor is1 pin pwm1 pwm2 dt1 dt2 table 9-6. top/bottom current-sense correction pin logic state output control is1 0 pmval1 controls pwm1/pwm2 pair 1 pmval2 controls pwm1/pwm2 pair is2 0 pmval3 controls pwm3/pwm4 pair 1 pmval4 controls pwm3/pwm4 pair is3 0 pmval5 controls pwm5/pwm6 pair 1 pmval6 controls pwm5/pwm6 pair pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 155 non-disclosure agreement required figure 9-23. internal correction logic wh en isens[1:0] = 10 figure 9-24. internal correction logic wh en isens[1:0] = 11 note: the values latched on the isx pins are buffered so t hat only one pwm register is used per pwm cycle. if a current sense value changes during a pwm period, the new va lue does not ta ke effect until the next pwm period. when initially enabled by setting th e pwmen bit, no current has previously been sensed. pw m value registers 1, 3, and 5 initially control the three pwm pairs when configur ed for current s ensing correction. dq clk pwm controlled by pwm controlled by deadtime generator dq clk isx pin a /b a b pwm cycle start top pwm bottom pwm initial value = 0 odd pwmval register even pwmval register dq clk pwm controlled by pwm controlled by deadtime generator dq clk isx pin a /b a b pwm cycle start top pwm bottom pwm initial value = 0 odd pwmval register even pwmval register pmcnt = pmmod non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 156 pulse width modulator for motor control (pwmmc) freescale semiconductor figure 9-25. correction with positive current figure 9-26. correction with negative current 9.6.4 output polarity the output polarity of the pwms is determined by two options: topneg and botneg. the top polarit y option, topneg, con trols the polarity of pwms 1, 3, and 5. the bottom polari ty option, botneg , controls the polarity of pwms 2, 4, and 6. positi ve polarity means that when the pwm is active, the pwm output is high . conversely, negative polarity means that when the pwm is active, pwm output is low. see figure 9-27 and section 5. configurat ion register (config) . note: both bits are found in the config register, which is a write-once register. this reduces the chances of the software inadvertently changing the polarity of the pwm si gnals and possibly damaging the motor drive hardware. desired load voltage bottom pwm load voltage top pwm desired load voltage bottom pwm load voltage top pwm pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 157 non-disclosure agreement required figure 9-27. pwm polarity up/down counter modulus = 4 pwm <= 0 pwm = 1 pwm = 2 pwm = 3 pwm >= 4 up-only counter modulus = 4 pwm <= 0 pwm = 1 pwm = 2 pwm = 3 pwm >= 4 center-aligned positive polarity edge-aligned positive polarity up/down counter modulus = 4 pwm <= 0 pwm = 1 pwm = 2 pwm = 3 pwm >= 4 up-only counter modulus = 4 pwm <= 0 pwm = 1 pwm = 2 pwm = 3 pwm >= 4 center-aligned negative polarity edge-aligned negative polarity non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 158 pulse width modulator for motor control (pwmmc) freescale semiconductor 9.6.5 output port control conditions may arise in which the pwm pins need to be individually controlled. this is made possible by the pwm output co ntrol register (pwmout) shown in figure 9-28 . if the outctl bit is set, the pwm pins can be controlled by the outx bits. these bits behave according to table 9-7 . when outctl is set, the polarity options toppol and botpol will still affect the outputs. in addition, if complement ary operation is in use, the pwm pairs will not be allowed to be active simultaneously, and dead- time will still not be violated. when outc tl is set and complimentary operation is in use, the odd outx bits are inputs to the dead-time generators as shown in figure 9-13 . dead-time is inserted whenever $0025bit 7654321bit 0 read: 0 outctl out6 out5 ou t4 out3 out2 out1 write: reset:00000000 = unimplemented figure 9-28. pwm output c ontrol register (pwmout) table 9-7. outx bits outx bit complementary mode independent mode out1 1 ? pwm1 is active 0 ? pwm1 is inactive 1 ? pwm1 is active 0 ? pwm1 is inactive out2 1 ? pwm2 is complement of pwm 1 0 ? pwm2 is inactive 1 ? pwm2 is active 0 ? pwm2 is inactive out3 1 ? pwm3 is active 0 ? pwm3 is inactive 1 ? pwm3 is active 0 ? pwm3 is inactive out4 1 ? pwm4 is complement of pwm 3 0 ? pwm4 is inactive 1 ? pwm4 is active 0 ? pwm4 is inactive out5 1 ? pwm5 is active 0 ? pwm5 is inactive 1 ? pwm5 is active 0 ? pwm5 is inactive out6 1 ? pwm 6 is complement of pwm 5 0 ? pwm6 is inactive 1 ? pwm6 is active 0 ? pwm6 is inactive pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 159 non-disclosure agreement required the odd outx bit toggles as shown in figure 9-29 . although dead-time is not inserted when the even outx bits change, ther e will be no dead- time violation as shown in figure 9-30 . setting the outctl bit does not di sable the pwm gener ator and current sensing circuitry. they continue to r un, but are no longer controlling the output pins. in add ition, outctl will control the pwm pins even when pwmen = 0. when outctl is cleared, the outputs of the pwm generator become the inputs to the dead-time and outp ut circuitry at the beginning of the next pwm cycle. note: to avoid an unexpected dead-time occurr ence, it is recommended that the outx bits be cleared prior to entering and prior to exiting individual pwm output control mode. 9.7 fault protection conditions may arise in the external drive circuitry which require that the pwm signals become inacti ve immediately, such as an overcurrent fault condition. furthermore, it may be desirable to selectively disable pwm(s) solely with software. one or more pwm pins c an be disabled (forced to their inactive state) by applying a logic high to any of the four external fault pins or by writing a logic high to either of the disabl e bits (disx and disy in pwm control register 1). figure 9-31 shows the structure of the pwm disabling scheme. while the pwm pi ns are disabled, they are forced to their inactive state. the pwm generator c ontinues to run ? only the output pins are disabled. non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 160 pulse width modulator for motor control (pwmmc) freescale semiconductor figure 9-29. dead-time i nsertion during outctl = 1 figure 9-30. dead-time i nsertion during outctl = 1 up/down counter modulus=4 pwm1 pwm2 dead-time = 2 outctl out1 out2 2 pwm1/pwm2 2 2 dead-time inserted as part of normal pwm operation as controlled by current sensing and pwm generator. dead-time inserted due to setting of out1 bit. dead-time inserted due to clearing of out1 bit. pwm value = 3 dead-time up/down counter modulus = 4 dead-time = 2 outctl pwm1 pwm2 out1 out2 2 pwm1/pwm2 2 2 pwm value = 3 dead-time inserted because when outctl was set, the state of out1 was such that pwm1 was directed to toggle dead-times inserted because out1 toggles, directing pwm1 to toggle. no dead-time inserted because out1 is not toggling. dead-time 2 MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width modulator for motor control (pwmmc) 161 pulse width modulator for motor control (pwmmc) non-disclosure agreement required figure 9-31. pwm disabli ng scheme (sheet 1 of 2) fault pin2 fint2 cycle start (logic high for fault) bank x disable fmode2 disx clear by writing 1 to ftack2 interrupt request two shot sq r sq r sq r sample filter one fpin2 fflag2 manual mode auto mode software x disable fault pin 2 disable the example is of fault pin 2 with disx. fault pin 4 with disy is logically similar and affects bank y disable. note: in manual mode (fmode = 0) fault 2 and 4 may be cleared only if a logic level low at the in put of the fault pin is present . non-disclosure agreement required technical data MC68HC708MP16 ? rev. 3.1 162 pulse width modulator for motor control (pwmmc) freescale semiconductor pulse width modulator for motor control (pwmmc) figure 9-32. pwm disabli ng scheme (sheet 2 of 2) fault pin1 fint1 cycle start (logic high for fault) bank x disable fmode1 clear by writing 1 to ftack1 interrupt request two shot sq r sq r sample filter one fflag1 manual mode auto mode fault pin 1 disable the example is of fault pin 1. fault pin 3 is logically similar and effects bank y disable. note: in manual mode (fmode = 0) fault 1 and 3 may be cleared regardless of the logic level at the input of the fault pin. fpin1 pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 163 non-disclosure agreement required to allow for different motor configur ations and the controlling of more than one motor, the pwm di sabling function is or ganized as two banks, bank x and bank y. bank information combines with information from the disable mapping register to allo w selective pwm disabling. fault pin 1, fault pin 2, and pwm disable bit x constitute the disabling function of bank x. fault pin 3, fault pin 4, and pwm disable bit y constitute the disabling functi on of bank y. figure 9-33 and figure 9-34 show the disable mapping write-once regist er and the decodi ng scheme of the bank which selectively disables pwm( s). when all bits of the disable mapping register ar e set, any disabl e condition will di sable all pwms. a fault can also generat e a cpu interrupt. each fault pin has its own interrupt vector. address: $0037 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 9-33. pw m disable mapping write-once register (dismap) non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 164 pulse width modulator for motor control (pwmmc) freescale semiconductor figure 9-34. pwm disabling decode scheme 9.7.1 fault condition input pins a logic high level on a fault pin disables t he respective pwm(s) determined by the bank and the disabl e mapping register. each fault pin incorporates a filter to assist in rejecting spur ious faults. all of the external fault pins ar e software-configurable to re-enable the pwms either with the fault pin (automatic mode) or with software (manual mode). each fault pin has an associat ed fmode bit to control the pwm re-enabling method . automatic mode is select ed by setting the fmodex bit in the fault control register. manual mode is selected when fmodex is clear. bit7 bit3 bit0 bit1 bit2 bit4 bit5 bit6 bank x disable disable disable disable disable disable disable disable bank y pwm pin 1 pwm pin 2 pwm pin 3 pwm pin 4 pwm pin 5 pwm pin 6 pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 165 non-disclosure agreement required 9.7.1.1 fault pin filter each fault pin incorporates a filter to assist in determining a genuine fault condition. after a fault pin has been l ogic low for one cpu cycle, a rising edge (logic high) w ill be synchronously samp led once per cpu cycle for two cycles. if both samp les are detected logic high, the corresponding fpin bit and fflag bit will be set. the fpin bit wil l remain set until the corresponding fault pin is logic lo w and synchronously sampled once in the following cpu cycle. 9.7.1.2 automatic mode in automatic mode, the pw m(s) are disabled imm ediately once a filtered fault condition is detec ted (logic high). the pwm(s ) remain disabled until the filtered fault condition is cl eared (logic low) and a new pwm cycle begins as shown in figure 9-35 . clearing the corresponding fflagx event bit will not enable t he pwms in automatic mode. figure 9-35. pwm disabling in automatic mode the filtered fault pins? logic state is reflected in th e respective fpinx bit. any write to this bit is overwritten by the pin state. the fflagx event bit is set with each rising edg e of the respective faul t pin after filtering has been applied. to clear the ffla gx bit, the user mu st write a 1 to the corresponding ftackx bit. pwm(s) pwm(s) enabled pwm(s) disabled (inactive) filtered fault pin non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 166 pulse width modulator for motor control (pwmmc) freescale semiconductor if the fintx bit is set, a fault c ondition resulting in setting the corresponding fflag bit will also latc h a cpu interrupt request. the interrupt request latch is not clear ed until one of t he following actions occurs: the fflagx bit is cleared by wr iting a 1 to th e corresponding ftackx bit. clearing the fintx bit. (this will not clear t he fflagx bit.) reset ? a reset automatically cl ears all four interrupt latches if prior to a vector fetc h, the interrupt request la tch is cleared by one of the above actions, a cpu interrupt wi ll no longer be requested. a vector fetch does not alter the state of the pwms, t he fflagx event flag or fintx. note: if the fflagx or fintx bits are not cleared duri ng the interrupt service routine, the inte rrupt request latch will not be cleared. 9.7.1.3 manual mode in manual mode, t he pwm(s) are disabled im mediately once a filtered fault condition is detec ted (logic high). the pwm(s ) remain disabled until software clears the corresponding fflagx event bi t and a new pwm cycle begins. in manual m ode, the fault pins are grouped in pairs, each pair sharing common functionality. a fault condition on pi ns 1 and 3 may be cleared, allowing the pwm(s) to enable at the start of a pwm cycle regardless of the logic leve l at the fault pin. see figure 9-36 . a fault condition on pins 2 and 4 can only be cleared, allowing the pwm(s) to enable, if a logic low level at the fault pin is present at the start of a pwm cycle. see figure 9-37 . pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 167 non-disclosure agreement required figure 9-36. pwm disabling in manual mode (example 1) figure 9-37. pwm disabling in manual mode (example 2) the function of the fault control and event bits is the same as in automatic mode except that the pwms are not re-enabled until the fflagx event bit is cleared by writ ing to the ftackx bit and the filtered fault condition is cleared (logic low). pwm(s) enabled pwm(s) enabled pwm(s) disabled fflagx cleared filtered fault pin 1 or 3 pwm(s) enabled pwm(s) enabled pwm(s) disabled fflagx cleared filtered fault pin 2 or 4 non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 168 pulse width modulator for motor control (pwmmc) freescale semiconductor 9.7.2 software output disable setting pwm disable bi t disx or disy in pw m control register 1 immediately disables the correspondi ng pwm pins as determined by the bank and disable mapping register. t he pwm pin(s) remain disabled until the pwm disable bit is clea red and a new pwm cycle begins as shown in figure 9-38 . setting a pwm disable bi t does not latch a cpu interrupt request, and ther e are no event flags as sociated with the pwm disable bits. 9.7.3 output port control when operating the pwms using the outx bits (outctl = 1), fault protection applies as described in this secti on. due to the absence of periodic pwm cycles, fault conditi ons are cleared u pon each cpu cycle and the pwm outputs ar e re-enabled, provided all fault clearing conditions are satisfied. figure 9-38. pwm software disable pwm(s) enabled pwm(s) enabled pwm(s) disabled disable bit pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 169 non-disclosure agreement required 9.8 initialization and the pwmen bit for proper operation, all r egisters should be initia lized and the ldok bit should be set before enabling the pwm via the pwmen bit. when the pwmen bit is first set, a reload will occur immediately, setting the pwmf flag and generating an interrupt if pwmi nt is set. in addition, in complementary mode, pwm value regist ers 1, 3, and 5 will be used for the first pwm cycle if current sens ing is selected. note: if the ldok bit is not set when pwmen is set after a reset , the prescaler and pwm values will be zero, but the modulus will be unknown. if the ldok bit is not set after the pwmen bit has been cleared then set (wit hout a reset), the modulus value that was last loaded will be used. if the dead-time regist er (deadtm) is c hanged after pwmen or outctl is set, an improper dead-time insertion could occur. however, the dead time can never be shor ter than the specified value. because of the equals-comparator ar chitecture of this pwm, the modulus = 0 case is cons idered illegal. therefore, the modulus register is not reset, and a modul us value of zero will result in waveforms inconsistent with the other modulus waveforms. see 9.11.2 pwm counter modulo registers . when pwmen is set, the pwm pins chan ge from hi-z to outputs. at this time, assuming no fault condition is present, t he pwm pins will drive according to the pwm values, polarit y, and dead-time. if the prescaler bits prsc1:prsc0 equal 00 (the default condition), the pwm pins will drive on the next cpu clo ck cycle, as shown by the timing diagram in figure 9-39 . note: the timing diagram in figure 9-39 is only applicable when prsc1:prsc0 = 00. if set to any other value, the pwm outputs will remain in the high-i mpedance condition for one complete pwm cycle before being driven. non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 170 pulse width modulator for motor control (pwmmc) freescale semiconductor figure 9-39. pw men and pwm pins when the pwmen bit is cleared, the following will occur: pwm pins will be tri- stated unless outctl = 1 pwm counter is cleared and will no t be clocked internally, the pwm generator will force its outputs to zero (to avoid glitches when th e pwmen is set again) when pwmen is cleared, the follow ing features remain active: all fault circuitry manual pwm pin control via the pwmout register dead-time insertion when pwm pins change via the pwmout register note: the pwmf flag and pendi ng cpu interrupts ar e not cleared when pwmen = 0. cpu clock pwmen pwm pins drive according to pwm value, polarity, and dead-time hi-z if outctl = 0 hi-z if outctl = 0 pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 171 non-disclosure agreement required 9.9 pwm operation in wait mode when the microcontroller is put in low-power wait mo de via the wait instruction, all clocks to the pwm module will c ontinue to run. if an interrupt is issued from the pwm modu le (via a reload or a fault), the microcontroller will exit wait mode. clearing the pwmen bit before enteri ng wait mode wi ll reduce power consumption in wait mode because the counter, presca ler divider, and ldfq divider will no longer be cl ocked. in additi on, power will be reduced because the pwms will no longer toggle. 9.10 pwm operation in break mode if the microcontroller goes into break mode (o r background mode), the clocks to the pwm generator and output control blocks will freeze. this allows the user to set a break point on a development system and examine the regist er contents and pwm outputs at that point. it also allows the user to si ngle-step through the code. the clocks to the fault bloc k will continue to run. therefor e, if a fault occurs while the microcontroller is in break mode, the pwm outputs will immediately be driven to th eir inactive state(s). during break mode, the system int egration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag cont rol register (sbfcr) enables software to clear status bits during t he break state. (see 7.7.4 sim break flag c ontrol register .) to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect the pwmf and fflagx bits during t he break state, make sure bcfe is a logic 0. with bcfe at logic 0 (its default state), software can read and write the status and cont rol registers during the break state without affecting the pwmf and fflagx bits. non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 172 pulse width modulator for motor control (pwmmc) freescale semiconductor 9.11 control logic block the following subsections provide a description of the control logic block. 9.11.1 pwm counter registers this pwm counter regist er displays the12-bi t up/down or up-only counter. when the high byte of the counter is read, the lower byte is latched. pcntl will ho ld this latched va lue until it is read. pcnth $0026bit 7654321bit 0 read: 000011109bit 8 write: reset:00000000 pcntl $0027 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 9-40. pwm counter registers (pcnth:pcntl) pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 173 non-disclosure agreement required 9.11.2 pwm counter modulo registers this pwm counter modulus register holds a 12-bi t unsigned number that determines the maximum count for the up/down or up-only counter. in center-aligned mode, t he pwm period will be twice the modulus (assuming no prescaler) . in edge-align ed mode, the pw m period will equal the modulus. to avoid erroneous pwm periods, this value is buffer ed and will not be used by the pwm generator until the ldok bit has been set and the next pwm load cycle begins. note: when reading this register , the value read is the buffer (not necessarily the value the pwm generator is currently using). caution: the user is responsible for initializing the pwm counter modulo registers before enabling the pwm module. since these r egisters are undefined at reset, they could contain a combined val ue of $0000, which would result in erroneous pulse widths. ho wever, the dead-tim e constraints will still be guaranteed, and t he fault detection circui try will still function properly. pmodh $0028bit 7654321bit 0 read: 0000 11 10 9 bit 8 write: reset:0000 xxxx pmodl $0029 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:xxxxxxxx = unimplemented figure 9-41. pwm counter m odulo registers (pdmodh:pmodl) non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 174 pulse width modulator for motor control (pwmmc) freescale semiconductor 9.11.3 pwm x value registers each of the six pwms has a 16-bit pwm value register. the 16-bit signed value stored in this register determi nes the duty cycle of the pwm. the duty cycle is defin ed as: (pwm val ue/modulus) x 100. writing a number less than or equal to zero caus es the pwm to be off for the entire pwm period. writing a nu mber greater than or equal to the 12-bit modulus causes the pwm to be on for the entire pwm period. if the complementary mode is se lected, the pwm pairs share pwm value registers. to avoid erroneous pwm pulses, this value is buffered and will not be used by the pwm generator until the ldok bit has been set and the next pwm load cycle begins. note: when reading these regi sters, the value read is the buffer (not necessarily the value the pwm g enerator is currently using). pvalxh bit 7 6 5 4 3 2 1 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 pvalxl bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 9-42. pwm x value re gisters (pvalxh:pvalxl) pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 175 non-disclosure agreement required 9.11.4 pwm control register 1 pwm control register 1 controls pw m enabling/disabling, the loading of new modulus, prescaler, and pwm values, and the pwm correction method. in addition, this register contains the software disable bits to force the pwm outputs to t heir inactive states (a ccording to the disable mapping register). pwmen ? pwm module enable this read/write bi t enables and disables the pwm generator and the pwm pins. when pwmen is clear, the pwm generator is disabled and the pwm pins are in the high-impedance state (unless outctl = 1). when the pwmen bit is set, the pwm generator and pwm pins are activated. for more information, see 9.8 initialization and the pwmen bit . 1 = pwm generator and pwm pins enabled 0 = pwm generator and pwm pins disabled ldok? load ok this write-only bit allows the count er modulus, counter prescaler, and pwm values in the buffered registers to be used by the pwm generator. these values will not be used until the ldok bit is set and a new pwm load cycle begins. intern ally this bit is automatically cleared after the new values are loaded (however, this bit always reads zero). 1 = okay to load new modulus, prescaler, and pwm values at beginning of nex t pwm load cycle 0 = not okay to load new modul us, prescaler, and pwm values address: $0020 bit 7654321bit 0 read: disx disy pwmint pwmf isens1 isens0 0 pwmen write: ldok reset:00000000 figure 9-43. pwm contro l register 1 (pctl1) non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 176 pulse width modulator for motor control (pwmmc) freescale semiconductor note: the user should initialize the pwm re gisters and set the ldok bit before enabling the pwm. a pwm cpu interrupt request can still be generated w hen ldok is zero. isens1:isens0 ? current sense correction bits these read/write bits select the top/bottom correction scheme as shown in table 9-8 . pwmf? pwm reload flag this read/write bit is set at the beginning of every reload cycle regardless of the state of the ldok bit. this bit is cleared by reading pwm control register 1 with the pwmf fl ag set, then writ ing a logic 0 to pwmf. if another reload occu rs before the clearing sequence is complete, then writing logic 0 to pwmf has no effect. 1 = new reload cycle began 0 = new reload cycle has not begun note: when pwmf is cleared, pending pwm cpu interrupts are cleared (not including fault interrupts). pwmint ? pwm interrupt enable this read/write bit allows the us er to enable and disable pwm cpu interrupts. if set, a cpu interrupt will be pending when the pwmf flag is set. 1 = enable pwm cpu interrupts 0 = disable pwm cpu interrupts table 9-8. correction methods current correction bits isens1:isens0 correction method 00 01 bits ipol1, ipol2, and ipol3 used for correction 10 current sensing on pins is1, is2, and is3 occurs during the dead-time. 11 current sensing on pins is1, is2, and is3 occurs at the half cycle in center-aligned mode and at the end of the cycle in edge-aligned mode. pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 177 non-disclosure agreement required note: when pwmint is cleared, pending cpu interrupts are inhibited. disx ? software disable for bank x this read/write bit allows the user to disable one or more pwm pins in bank x. the pins that are di sabled are determined by the disable mapping write-once register. 1 = disable pwm pi ns in bank x 0 = re-enable pwm pins at beginning of next pwm cycle disy ? software disable for bank y this read/write bit allows the user to disable one or more pwm pins in bank y. the pins that are di sabled are determined by the disable mapping write-once register. 1 = disable pwm pi ns in bank y 0 = re-enable pwm pins at beginning of next pwm cycle 9.11.5 pwm control register 2 pwm control register 2 controls the pwm load fr equency, the pwm correction method, and the pwm co unter prescaler. for ease of software and to avoid er roneous pwm periods, some of these register bits are buffered. the pwm generator will not us e the prescaler value until the ldok bit has been set, and a new pwm cycle is starting. the correction bits are used at the beginning of each pwm cycle (if the isensx bits are configur ed for software correc tion). the load frequency bits are not used until the current load cycle is complete. note: the user should initialize this register before enabling the pwm. address: $0021 bit 7654321bit 0 read: ldfq1 ldfq0 0 ipol1 ipol2 ipol3 prsc1 prsc0 write: reset:00000000 = unimplemented figure 9-44. pwm contro l register 2 (pctl2) non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 178 pulse width modulator for motor control (pwmmc) freescale semiconductor ldfq1:ldfq0 ? pwm load frequency bits these buffered read/write bits se lect the pwm cp u load frequency according to table 9-9 . note: when reading these bits, the valu e read is the buffer value (not necessarily the value the pwm g enerator is currently using). ipol1 ? top/bottom correction bi t for pwm pair 1 (pwms 1 and 2) this buffered read/write bit selects which pwm value register is used if top/bottom correction is to be achieved without current sensing. 1 = use pwm val ue register 2 0 = use pwm val ue register 1 note: when reading this bit, the value read is the buffer value (not necessarily the value the output control block is currently using). ipol2 ? top/bottom correction bi t for pwm pair 2 (pwms 3 and 4) this buffered read/write bit selects which pwm value register is used if top/bottom correction is to be achieved without current sensing. 1 = use pwm val ue register 4 0 = use pwm val ue register 3 note: when reading this bit, the value read is the buffer value (not necessarily the value the output control block is currently using). ipol3 ? top/bottom correction bi t for pwm pair 3 (pwms 5 and 6) this buffered read/write bit selects which pwm value register is used if top/bottom correction is to be achieved without current sensing. 1 = use pwm val ue register 6 0 = use pwm val ue register 5 table 9-9. pwm reload frequency reload frequency bits ldfq1:ldfq0 pwm reload frequency 00 every pwm cycle 01 every 2 pwm cycles 10 every 4 pwm cycles 11 every 8 pwm cycles pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 179 non-disclosure agreement required note: when reading this bit, the value read is the buffer value (not necessarily the value the output control block is currently using). prsc1:prsc0 ? pwm prescaler bits these buffered read/write bits allo w the pwm clock frequency to be modified as shown in table 9-10 . note: when reading these bits, the valu e read is the buffer value (not necessarily the value the pwm g enerator is currently using). table 9-10 . pwm prescaler 9.11.6 dead-time write-once register this write-once register holds an 8-bi t value which specifies the number of cpu clock cycles to use for t he dead-time when co mplementary pwm mode is selected. after this register is written for the first time, it cannot be rewritten unless a reset occurs. the dead-time is not affected by changes to the pr escaler value. prescaler bits prsc1:prsc0 pwm clock frequency 00 f op 01 f op /2 10 f op /4 11 f op /8 address: $0036 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 9-45. dead-time writ e-once register (deadtm) non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 180 pulse width modulator for motor control (pwmmc) freescale semiconductor 9.11.7 pwm disable mapping write-once register this write-once register holds an 8- bit value which determines which pwm pins will be disabled if an external fault or software disable occur. for a further description of the disable mapping, see 9.7 fault protection . after this register is written for the first time, it cannot be rewritten unless a reset occurs. 9.11.8 fault control register this register cont rols the fault pr otection circuitry. fmode1 ? fault mode selection fo r fault pin 1 (automatic versus manual mode) this read/write bit allo ws the user to select between automatic and manual mode faults . for further description of each mode, see 9.7 fault protection . 1 = automatic mode 0 = manual mode address: $0037 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 9-46. pwm disable mappi ng write-once register (dismap) address: #0022 bit 7654321bit 0 read: fint4fmode4fint3fmode3fint2fmode2fint1fmode1 write: reset:00000000 figure 9-47. fault cont rol register (fcr) pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 181 non-disclosure agreement required fint1 ? fault 1 interrupt enable this read/write bit allows the cpu interrupt caus ed by faults on fault pin 1 to be enabled. the fault protec tion circuitry is independent of this bit and will always be active. if a f ault is detected, the pwm pins will still be disabled according to the disable mapping register. 1 = fault pin 1 will c ause cpu interrupts 0 = fault pin 1 will not cause cpu interrupts fmode2 ? fault mode selection fo r fault pin 2 (automatic versus manual mode) this read/write bit allo ws the user to select between automatic and manual mode faults . for further description of each mode, see 9.7 fault protection . 1 = automatic mode 0 = manual mode fint2 ? fault 2 interrupt enable this read/write bit allows the cpu interrupt caus ed by faults on fault pin 2 to be enabled. the fault protec tion circuitry is independent of this bit and will always be active. if a f ault is detected, the pwm pins will still be disabled according to the disable mapping register. 1 = fault pin 2 will c ause cpu interrupts 0 = fault pin 2 will not cause cpu interrupts fmode3 ? fault mode selection fo r fault pin 3 (automatic versus manual mode) this read/write bit allo ws the user to select between automatic and manual mode faults . for further description of each mode, see 9.7 fault protection . 1 = automatic mode 0 = manual mode non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 182 pulse width modulator for motor control (pwmmc) freescale semiconductor fint3 ? fault 3 interrupt enable this read/write bit allows the cpu interrupt caus ed by faults on fault pin 3 to be enabled. the fault protec tion circuitry is independent of this bit and will always be active. if a f ault is detected, the pwm pins will still be disabled according to the disable mapping register. 1 = fault pin 3 will c ause cpu interrupts 0 = fault pin 3 will not cause cpu interrupts fmode4 ? fault mode selection fo r fault pin 4 (automatic versus manual mode) this read/write bit allo ws the user to select between automatic and manual mode faults . for further description of each mode, see 9.7 fault protection . 1 = automatic mode 0 = manual mode fint4 ? fault 4 interrupt enable this read/write bit allows the cpu interrupt caus ed by faults on fault pin 4 to be enabled. the fault protec tion circuitry is independent of this bit and will always be active. if a f ault is detected, the pwm pins will still be disabled according to the disable mapping register. 1 = fault pin 4 will c ause cpu interrupts 0 = fault pin 4 will not cause cpu interrupts pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 183 non-disclosure agreement required 9.11.9 fault status register this read-only register indicate s the current fault status. fflag1 ? fault event flag 1 the fflag1 event bit is set within two cpu cycles after a rising edge on fault pin 1. to clear the fflag1 bit, the user must write a 1 to the ftack1 bit in the faul t acknowledge register. 1 = a fault has occu rred on fault pin 1 0 = no new faul t on fault pin 1 fpin1 ? state of fault pin 1 this read-only bit a llows the user to read t he current stat e of fault pin 1. 1 = fault pin 1 is at logic 1 0 = fault pin 1 is at logic 0 fflag2 ? fault event flag 2 the fflag2 event bit is set within two cpu cycles after a rising edge on fault pin 2. to clear the fflag2 bit, the user must write a 1 to the ftack2 bit in the faul t acknowledge register. 1 = a fault has occu rred on fault pin 2 0 = no new faul t on fault pin 2 fpin2 ? state of fault pin 2 this read-only bit a llows the user to read t he current stat e of fault pin 2. 1 = fault pin 2 is at logic 1 0 = fault pin 2 is at logic 0 address: $0023 bit 7 6 54 321bit 0 read: fpin4 fflag4 fpin3 fflag3 fpin2 fflag2 fpin1 fflag1 write: reset:u0u0u0u0 = unimplemented u = unaffected figure 9-48. fault st atus register (fsr) non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 184 pulse width modulator for motor control (pwmmc) freescale semiconductor fflag3 ? fault event flag 3 the fflag3 event bit is set within two cpu cycles after a rising edge on fault pin 3. to clear the fflag3 bit, the user must write a 1 to the ftack3 bit in the faul t acknowledge register. 1 = a fault has occu rred on fault pin 3 0 = no new faul t on fault pin 3 fpin3 ? state of fault pin 3 this read-only bit a llows the user to read t he current stat e of fault pin 3. 1 = fault pin 3 is at logic 1 0 = fault pin 3 is at logic 0 fflag4 ? fault event flag 4 the fflag4 event bit is set within two cpu cycles after a rising edge on fault pin 4. to clear the fflag4 bit, the user must write a 1 to the ftack4 bit in the faul t acknowledge register. 1 = a fault has occu rred on fault pin 4 0 = no new faul t on fault pin 4 fpin4 ? state of fault pin 4 this read-only bit a llows the user to read t he current stat e of fault pin 4. 1 = fault pin 4 is at logic 1 0 = fault pin 4 is at logic 0 pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 185 non-disclosure agreement required 9.11.10 fault acknowledge register this register is used to acknowledge and clear t he fflags. in addition, it is used to monitor the current s ensing bits to test proper operation. ftack1 ? fault acknowledge 1 the ftack1 bit is used to acknowl edge and clear fflag1. this bit will always read 0. writing a 1 to th is bit will clear fflag1. writing a 0 will have no effect. ftack2 ? fault acknowledge 2 the ftack2 bit is used to acknowl edge and clear fflag2. this bit will always read 0. writing a 1 to th is bit will clear fflag2. writing a 0 will have no effect. ftack3 ? fault acknowledge 3 the ftack3 bit is used to acknowl edge and clear fflag3. this bit will always read 0. writing a 1 to th is bit will clear fflag3. writing a 0 will have no effect. ftack4 ? fault acknowledge 4 the ftack4 bit is used to acknowl edge and clear fflag4. this bit will always read 0. writing a 1 to th is bit will clear fflag4. writing a 0 will have no effect. dt1 ? dead time 1 current sensing pin is1 is monito red immediately before dead time ends due to the assertion of pwm1. address: $0024 bit 7654321bit 0 read: 0 0 dt6 dt5 dt4 dt3 dt2 dt1 write: ftack4 ftack3 ftack2 ftack1 reset:00000000 = unimplemented figure 9-49. fault acknow ledge register (ftack) non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 186 pulse width modulator for motor control (pwmmc) freescale semiconductor dt1 ? dead time 2 current sensing pin is1 is monito red immediately before dead time ends due to the assertion of pwm2. dt1 ? dead time 3 current sensing pin is2 is monito red immediately before dead time ends due to the assertion of pwm3. dt1 ? dead time 4 current sensing pin is2 is monito red immediately before dead time ends due to the assertion of pwm4. dt1 ? dead time 5 current sensing pin is3 is monito red immediately before dead time ends due to the assertion of pwm5. dt1 ? dead time 6 current sensing pin is3 is monito red immediately before dead time ends due to the assertion of pwm6. 9.11.11 pwm output control register this register is used to m anually control the pwm pins. outctl? output control enable this read/write bit allows the user to manually control the pwm pins. when set, the pwm generator is no l onger the input to the dead-time and output circuitry. the outx bits determine the state of the pwm pins. setting the outc tl bit does not dis able the pwm generator. $0025bit 7654321bit 0 read: 0 outctl out6 out5 out4 out3 out2 out1 write: reset:00000000 = unimplemented figure 9-50. pwm output c ontrol register (pwmout) pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 187 non-disclosure agreement required the generator continues to run, but is no longer the input to the pwm dead-time and output circuitry. w hen outctl is cleared, the outputs of the pwm generator im mediately become the inputs to the dead- time and output circuitry. 1 = pwm outputs co ntrolled manually 0 = pwm outputs determ ined by pwm generator out6:out1? pwm pin output control bits these read/write bits control the pwm pins according to table 9-11 . table 9-11. outx bits outx bit complementary mode independent mode out1 1 ? pwm1 is active 0 ? pwm1 is inactive 1 ? pwm1 is active 0 ? pwm1 is inactive out2 1 ? pwm2 is complement of pwm 1 0 ? pwm2 is inactive 1 ? pwm2 is active 0 ? pwm2 is inactive out3 1 ? pwm3 is active 0 ? pwm3 is inactive 1 ? pwm3 is active 0 ? pwm3 is inactive out4 1 ? pwm4 is complement of pwm 3 0 ? pwm4 is inactive 1 ? pwm4 is active 0 ? pwm4 is inactive out5 1 ? pwm5 is active 0 ? pwm5 is inactive 1 ? pwm5 is active 0 ? pwm5 is inactive out6 1 ? pwm 6 is complement of pwm 5 0 ? pwm6 is inactive 1 ? pwm6 is active 0 ? pwm6 is inactive non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 188 pulse width modulator for motor control (pwmmc) freescale semiconductor 9.12 pwm glossary cpu cycle ? one internal bus cycle (1/f op ) pwm clock cycle (or period) ? one tick of the pwm counter (1/f op with no prescaler). see figure 9-51 . pwm cycle (or period) center-aligned mode: the time it takes the pwm counter to count up and count down (modulus*2/f op assuming no prescaler). see figure 9-51 . edge-aligned mode: th e time it takes the pwm counter to count up (modulus/f op ). see figure 9-51 . figure 9-51. pwm clock cycle and pwm cycle definitions pwm clock cycle pwm cycle (or period) pwm pwm cycle (or period) center-aligned mode edge-aligned mode clock cycle pulse width modulator for motor control (pwmmc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor pulse width mo dulator for motor control (pwmmc) 189 non-disclosure agreement required pwm load frequency ? frequency at which new pwm parameters get loaded into the pwm. see figure 9-52 . figure 9-52. pwm load c ycle/frequency definition reload new modulus, prescaler, & pwm values if ldok = 1 reload new modulus, prescaler, & pwm values if ldok = 1 pwm load cycle ldfq1:ldfq0 = 01 ? reload every two cycles (1/pwm load frequency) non-disclosure agreement required pulse width modulator for motor control (pwmmc) technical data MC68HC708MP16 ? rev. 3.1 190 pulse width modulator for motor control (pwmmc) freescale semiconductor MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor monitor rom (mon) 191 non-disclosure agreement required technical data ? MC68HC708MP16 section 10. monitor rom (mon) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 10.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 10.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 10.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 10.2 introduction this section describes the moni tor rom (mon08, version b). the monitor rom allows complete testin g of the mcu thro ugh a single-wire interface with a host computer. non-disclosure agreement required monitor rom (mon) technical data MC68HC708MP16 ? rev. 3.1 192 monitor rom (mon) freescale semiconductor 10.3 features features of the monitor rom include the following: normal user-mode pin functionality one pin dedicated to serial co mmunication between monitor rom and host computer standard mark/space non-return -to-zero (nrz) communication with host computer 4800 baud?28.8 kbaud communication wi th host computer execution of code in ram or rom (e)eprom/otprom programming 10.4 functional description the monitor rom receives and exec utes commands from a host computer. figure 10-1 shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can exec ute host-computer code in ram while all mcu pins retain normal operating mode functions. all communication between the host computer and the m cu is through the pta0 pin. a level-shifting and multiplexing in terface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pull-up resistor. monitor rom (mon) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor monitor rom (mon) 193 non-disclosure agreement required figure 10-1. moni tor mode circuit + + + + 10 m ? x1 v dd v dd + v hi mc145407 mc74hc125 68hc708 rst irq1 /v pp cgmxfc osc1 osc2 v ss a v ss v dd pta0 v dd 10 k ? 0.1 f 0.1 f 10 ? 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 20 pf 20 pf 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f 4.9152 mhz 10 k ? ptc2 v dd 10 k ? b a notes: position a ? bus clock = cgmxclk 4 or cgmvclk 4 position b ? bus clock = cgmxclk 2 (see note.) 5 6 pwmgnd v ss ad v refl v dd a 0.1 f v dd a v dd ad 0.1 f v dd ad v adcap 0.1 f v adcap ptc3 ptc4 v dd 10 k ? non-disclosure agreement required monitor rom (mon) technical data MC68HC708MP16 ? rev. 3.1 194 monitor rom (mon) freescale semiconductor 10.4.1 entering monitor mode table 10-1 shows the pin conditions for entering monitor mode. enter monitor mode by either: executing a software inte rrupt instruction (swi) or applying a logic 0 and t hen a logic 1 to the rst pin. the mcu sends a break si gnal (10 consecutive lo gic 0s) to the host computer, indicating that it is ready to receive a command. the break signal also provides a timing referenc e to allow the host to determine the necessary baud rate. monitor mode uses alternat e vectors for reset, sw i, and break interrupt. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. the cop module is disabled in monitor mode as long as v dd +v hi is applied to either the irq1 /v pp pin or the rst pin. (see section 7. system int egration module (sim) for more information on modes of operation.) note: holding the ptc2 pin low when ent ering monitor mode causes a bypass of a divide-by-two stage at the oscillator. the cgmout frequency is equal to the cgmxclk frequency, and the osc1 i nput directly generates internal bus clocks. in th is case, the osc1 signal must have a 50% duty cycle at maximum bus frequency. table 10-1. mode selection irq1 /v pp pin ptc3 pin ptc4 pin pta0 pin ptc2 pin mode cgmout bus frequency v dd + v hi 1011 monitor or v dd + v hi 1010 monitor cgmxclk cgmxclk 2 ----------------------------- cgmvclk 2 ----------------------------- cgmout 2 -------------------------- cgmout 2 -------------------------- monitor rom (mon) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor monitor rom (mon) 195 non-disclosure agreement required table 10-2 is a summary of the differ ences between user mode and monitor mode. 10.4.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. (see figure 10-2 and figure 10-3 .) figure 10-2. moni tor data format figure 10-3. sample monitor waveforms the data transmit and receive rate can be anywhere fr om 4800 baud to 28.8 kbaud. transmit and receive baud rates must be identical. table 10-2. mode differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) 1. if the high voltage (v dd + v hi ) is removed from the irq1 /v pp pin or the rst pin, the sim asserts its cop enable output. the cop is a mask option enabled or disabled by the copd bit in the mask option register. $fefe $feff $fefc $fefd $fefc $fefd bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 next stop bit start bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7 non-disclosure agreement required monitor rom (mon) technical data MC68HC708MP16 ? rev. 3.1 196 monitor rom (mon) freescale semiconductor 10.4.3 echoing as shown in figure 10-4 , the monitor rom immediately echoes each received byte back to the pt a0 pin for error checking. figure 10-4. read transaction any result of a command appears after the ec ho of the last byte of the command. 10.4.4 break signal a start bit followed by nine low bits is a break signal. (see figure 10-5 .) when the monitor receives a break sign al, it drives the pta0 pin high for the duration of tw o bits before echoi ng the break signal. figure 10-5. break transaction addr. high read read addr. high addr. low addr. low data echo sent to monitor result 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo monitor rom (mon) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor monitor rom (mon) 197 non-disclosure agreement required 10.4.5 commands the monitor rom uses t he following commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) table 10-3. read (r ead memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence addr. high read read addr. high addr. low addr. low data echo sent to monitor result non-disclosure agreement required monitor rom (mon) technical data MC68HC708MP16 ? rev. 3.1 198 monitor rom (mon) freescale semiconductor table 10-4. write (write memory) command description write byte to memory operand specifies 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence addr. high write write addr. high addr. low addr. low data echo sent to monitor data table 10-5. iread (i ndexed read) command description read next 2 bytes in me mory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence data iread iread data echo sent to monitor result monitor rom (mon) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor monitor rom (mon) 199 non-disclosure agreement required note: a sequence of iread or iwrite commands can sequentially access a block of memory over the full 64-kbyte memory map. table 10-6. iwrite (indexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence data iwrite iwrite data echo sent to monitor table 10-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence sp high readsp readsp sp low echo sent to monitor result non-disclosure agreement required monitor rom (mon) technical data MC68HC708MP16 ? rev. 3.1 200 monitor rom (mon) freescale semiconductor 10.4.6 baud rate with a 4.9152-mhz crystal and the ptc2 pin at logic 1 during reset, data is transferred between t he monitor and host at 480 0 baud. if the ptc2 pin is at logic 0 during reset, the monitor baud rate is 9600. when the cgm output, cgmout, is driven by the pll, the baud rate is determined by the mul[7: 4] bits in the pll pr ogramming register (ppg). (see section 8. clock g enerator module (cgm) .) table 10-8. run (run u ser program) command description executes rti instruction operand none data returned none opcode $28 command sequence run run echo sent to monitor table 10-9. monitor baud rate selection vco frequency multiplier (n) 123456 monitor baud rate 4800 9600 14,400 19,200 24,000 28,800 MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module a (tima) 201 non-disclosure agreement required technical data ? MC68HC708MP16 section 11. timer interface module a (tima) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 11.4.1 tima counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . 205 11.4.2 input capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 11.4.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 11.4.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 206 11.4.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .207 11.4.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . 207 11.4.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 209 11.4.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 210 11.4.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 11.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 11.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 11.7 tima during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . . 213 11.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 11.8.1 tima clock pin (pte0/ tclka). . . . . . . . . . . . . . . . . . . . . 213 11.8.2 tima channel i/o pins (pte1/tch0a:pte2/tch1a) . . . . . . . . . . . . . . . . . . . 214 11.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 11.9.1 tima status and cont rol register. . . . . . . . . . . . . . . . . . . 215 11.9.2 tima counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . 217 11.9.3 tima counter modulo registers . . . . . . . . . . . . . . . . . . . .218 11.9.4 tima channel status and control registers . . . . . . . . . . 219 11.9.5 tima channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . 223 non-disclosure agreement required timer interface module a (tima) technical data MC68HC708MP16 ? rev. 3.1 202 timer interface module a (tima) freescale semiconductor 11.2 introduction this section describes the timer inte rface module (tim2, version b). the tima is a two-channel timer that pr ovides a timing reference with input capture, output compar e, and pulse-width-m odulation functions. figure 11-1 is a block diagr am of the tim. note: timer interface module a (tima) is onl y available in the 64-pin quad flat package. 11.3 features features of the tima include the following: two input capture/ou tput compare channels ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable tima clock input ? seven-frequency internal bus clock prescaler selection ? external tima clock inpu t (4-mhz maximum frequency) free-running or modul o up-count operation toggle any channel pin on overflow tima counter stop and reset bits modular architecture expandable to eight channels 11.4 functional description figure 11-1 shows the structure of the tima. the central component of the tima is the 16-bit tima counte r that can operat e as a free-running counter or a modulo up-c ounter. the tima counter provides the timing reference for the input capture and output compare functions. the tima counter modulo registers, tamodh:t amodl, control the modulo value timer interface module a (tima) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module a (tima) 203 non-disclosure agreement required of the tima counter. software can re ad the tima counter value at any time without affectin g the counting sequence. the two tima channels are progra mmable independently as input capture or output compare channels. figure 11-1. tima block diagram prescaler prescaler select tclk internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tach0h:tach0l ms0a els0b els0a pte1 tof toie inter- 16-bit comparator 16-bit latch tach1h:tach1l channel 0 channel 1 tamodh:tamodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus bus clock ms1a pte0/tclka pte1/tch0a pte2/tch1a logic rupt logic inter- rupt logic pte2 logic inter- rupt logic non-disclosure agreement required timer interface module a (tima) technical data MC68HC708MP16 ? rev. 3.1 204 timer interface module a (tima) freescale semiconductor addr. name bit 7 6 5 4 3 2 1 bit 0 $000c timer a status and control register (tasc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 0 0 1 0 0 0 0 0 $000d timer a counter register high (tacnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $000e timer a counter register low (tacntl) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $000f timer a modulo register high (tamodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0010 timer a modulo register low (tamodl) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0011 timer a channel 0 status and control register (tasc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 $0012 timer a channel 0 register high (tach0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0013 timer a channel 0 register low (tach0l) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0014 timer a channel 1 status and control register (tasc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 0 0 0 0 0 0 0 0 = unimplemented figure 11-2. tima i/ o register summary timer interface module a (tima) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module a (tima) 205 non-disclosure agreement required 11.4.1 tima counter prescaler the tima clock source can be one of the seven prescaler outputs or the tima clock pin, pte0/tclka. the prescaler generat es seven clock rates from the internal bus clock. the prescaler se lect bits, ps[2:0], in the tima status and co ntrol register select the tima clock source. 11.4.2 input capture with the input capture function, the tima can capture th e time at which an external event occurs . when an active edge o ccurs on the pin of an input capture channel, the tima la tches the contents of the tima counter into the tima channel regi sters, tachxh:tachxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 11.4.3 output compare with the output compare function, the tima can generate a periodic pulse with a progr ammable polarity, duration, and frequency. when the counter reaches the value in the r egisters of an output compare channel, the tima can se t, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. $0015 timer a channel 1 register high (tach1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0016 timer a channel 1 register low (tach1l) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset addr. name bit 7 6 5 4 3 2 1 bit 0 = unimplemented figure 11-2. tima i/o r egister summary (continued) non-disclosure agreement required timer interface module a (tima) technical data MC68HC708MP16 ? rev. 3.1 206 timer interface module a (tima) freescale semiconductor 11.4.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 11.4.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the ol d value currently in th e tima channel registers. an unsynchronized write to the tima channel registers to change an output compare value could cause incorrect operati on for up to two counter overflow periods. for exampl e, writing a new value before the counter reaches the old value but after the c ounter reaches the new value prevents any compare during that counter overflow period. also, using a tima overflow interrupt rout ine to write a new , smaller output compare value may caus e the compare to be missed. the tima may pass the new value bef ore it is written. use the following methods to synch ronize unbuffered changes in the output compare va lue on channel x: when changing to a smaller va lue, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse . the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare val ue, enable channel x tima overflow inte rrupts and write the new value in the tima overflow interrupt routine. the tima overflow interrupt occurs at the end of the cu rrent counter overflow per iod. writing a larger value in an output co mpare interrupt routin e (at the end of the current pulse) could c ause two output compar es to occur in the same counter overflow period. timer interface module a (tima) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module a (tima) 207 non-disclosure agreement required 11.4.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appe ars on the pte1/tch0 a pin. the tima channel registers of th e linked pair alternatel y control the output. setting the ms0b bit in tima channe l 0 status and control register (tasc0) links channel 0 and channel 1. the output compare value in the tima channel 0 regist ers initially controls the output on the pte1/tch0a pin. writing to the tima channel 1 registers enables the tima channel 1 registers to synchr onously control the output after the tima overflows. at each subseque nt overflow, the tima channel registers (0 or 1) that control the output are t he ones written to last. tasc0 controls and monitors the buf fered output compar e function, and tima channel 1 status and control regi ster (tasc1) is unused. while the ms0b bit is set, the channel 1 pin, pte2/tch1a, is available as a general-purpose i/o pin. note: in buffered output compare operati on, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares. 11.4.4 pulse width modulation (pwm) by using the toggle-on-overflow f eature with an output compare channel, the tima can generate a pwm signal. the value in the tima counter modulo registers determi nes the period of th e pwm signal. the channel pin toggles when the counter reaches the value in the tima counter modulo registers. the time between ov erflows is the period of the pwm signal. as figure 11-3 shows, the output compare value in the tima channel registers determines t he pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tima to clear the channel pin on output compare if the state of the pwm pulse is logic 1. program the tima to set the pin if the state of the pwm pulse is logic 0. non-disclosure agreement required timer interface module a (tima) technical data MC68HC708MP16 ? rev. 3.1 208 timer interface module a (tima) freescale semiconductor figure 11-3. pwm peri od and pulse width the value in the tima counter m odulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is va riable in 256 in crements. writing $00ff (255) to the tima counter modulo regi sters produces a pwm period of 256 times the in ternal bus clock period if the prescaler select value is 000 (see 11.9.1 tima status and control register ). the value in the tima channel regist ers determines the pulse width of the pwm output. the puls e width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tima channel registers produces a duty cycl e of 128/256 or 50%. ptex/tchxa period pulse width overflow overflow overflow output compare output compare output compare timer interface module a (tima) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module a (tima) 209 non-disclosure agreement required 11.4.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 11.4.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currentl y in the tima channel registers. an unsynchronized write to the tima channel registers to change a pulse width value coul d cause incorrect operat ion for up to two pwm periods. for example, writing a ne w value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a ti ma overflow interrupt routine to write a new, smaller pulse width val ue may cause the compare to be missed. the tima may pass the new valu e before it is written. use the following methods to synch ronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pu lse. the interrupt routi ne has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable channel x tima overflow interrupts and write the new value in the tima overflow interrupt routine. the tima overflow interrupt occurs at the end of the current pwm period. writin g a larger value in an output compare interrupt routine (at t he end of the curr ent pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. non-disclosure agreement required timer interface module a (tima) technical data MC68HC708MP16 ? rev. 3.1 210 timer interface module a (tima) freescale semiconductor 11.4.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the pte1 /tch0a pin. the tima channel registers of the linked pair alternately contro l the pulse width of the output. setting the ms0b bit in tima channe l 0 status and control register (tasc0) links channel 0 and channel 1. the tima channel 0 registers initially control the pulse width on the pte1/tch0a pin. writing to the tima channel 1 regist ers enables the tima channel 1 regi sters to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tima channel registers (0 or 1) that control the pul se width are the ones written to last. tasc0 controls and monitors the buffer ed pwm function, and tima channel 1 status and control register (tasc1) is unused. while the ms0b bit is set, the channel 1 pin, pte2/tch1a, is available as a general-purpose i/o pin. note: in buffered pwm signal gener ation, do not write new pulse width values to the currently active channel registers. writi ng to the acti ve channel registers is the same as gen erating unbuffe red pwm signals. 11.4.4.3 pwm initialization to ensure correct operation when gen erating unbuffered or buffered pwm signals, use the follow ing initializat ion procedure: 1. in the tima status and control register (tasc): a. stop the tima counter by sett ing the tima stop bit, tstop. b. reset the tima counter by sett ing the tima re set bit, trst. 2. in the tima counter modulo r egisters (tamodh:tamodl), write the value for the required pwm period. 3. in the tima channel x registers (tachxh :tachxl), write the value for the requ ired pulse width. timer interface module a (tima) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module a (tima) 211 non-disclosure agreement required 4. in tima channel x status and contro l register (tascx): a. write 0:1 (for unbuffered outp ut compare or pwm signals) or 1:0 (for buffered outp ut compare or pwm si gnals) to the mode select bits, msxb:msxa. (see table 11-2 .) b. write 1 to the toggle- on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level se lect bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 11-2 .) note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tima stat us control register (tasc) , clear the ti ma stop bit, tstop. setting ms0b links chann els 0 and 1 and configur es them for buffered pwm operation. the tima channel 0 registers (tach0h:tach0l) initially control the buff ered pwm output. tima st atus control register 0 (tascr0) controls and monitors t he pwm signal fr om the linked channels. ms0b takes pr iority over ms0a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tima overflows. subsequen t output compares try to force the output to a state it is already in and have no effect. the resu lt is a 0% duty cycle output. setting the channel x maximum dut y cycle bit (chxm ax) and clearing the tovx bit generates a 100% duty cycle output. (see 11.9.4 tima channel status and c ontrol registers .) non-disclosure agreement required timer interface module a (tima) technical data MC68HC708MP16 ? rev. 3.1 212 timer interface module a (tima) freescale semiconductor 11.5 interrupts the following tima sources can generate interrupt requests: tima overflow flag (tof) ? the to f bit is set when the tima counter value rolls over to $0000 after matching t he value in the tima counter modulo registers. the tima overflow interrupt enable bit, toie, enables tima overflow cpu interrupt requests. tof and toie are in the tima status a nd control register. tima channel flags (ch1f:ch0f) ? the chxf bit is set when an input capture or output compar e occurs on channel x. channel x tim cpu interrupt requests ar e controlled by the channel x interrupt enable bit, chxie. c hannel x tim cpu interrupt requests are enabled when chxie = 1. chxf and chxi e are in the tima channel x status and control register. 11.6 wait mode the wait instruction puts the mcu in low-power-consumption standby mode. the tima remains active af ter the execution of a wait instruction. in wait mode the tima registers ar e not accessible by the cpu. any enabled cpu interrupt reque st from the tima can bring the mcu out of wait mode. if tima functions are not requir ed during wait mode, reduce power consumption by stoppi ng the tima before ex ecuting the wait instruction. timer interface module a (tima) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module a (tima) 213 non-disclosure agreement required 11.7 tima during break interrupts a break interrupt stops the tima counter. the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during t he break state. (see 7.7.4 sim break flag control register .) to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect status bits du ring the break state, writ e a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), software can read and write i/o registers during the break state wi thout affecting status bits. some status bits have a two-step read/wr ite clearing proce dure. if software does the first step on su ch a bit before the br eak, the bit cannot change during the break state as long as bcf e is at logic 0. after the break, doing the second step cl ears the status bit. 11.8 i/o signals port e shares three of its pins with the tima. pte0/tclka is an external clock input to the tima prescaler. the two tima channel i/o pins are pte1/tch0a and pte2/tch1a. 11.8.1 tima clock pin (pte0/tclka) pte0/tclka is an external clock inpu t that can be the clock source for the tima counter instead of the presca led internal bus clock. select the pte0/tclka input by writ ing logic 1s to the thr ee prescaler select bits, non-disclosure agreement required timer interface module a (tima) technical data MC68HC708MP16 ? rev. 3.1 214 timer interface module a (tima) freescale semiconductor ps[2:0]. (see 11.9.1 tima status and control register .) the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is: bus frequency 2 pte0/tclka is avail able as a general-purpose i/o pin when not used as the tima clock input . when the pte0/tclka pi n is the tima clock input, it is an input regardless of the state of the ddre0 bit in data direction register e. 11.8.2 tima channel i/o pins (pte1/tch0a:pte2/tch1a) each channel i/o pin is progr ammable independently as an input capture pin or an output compare pin. pte1/tch0a and pte2/tch1a can be configured as buffered output compare or buffered pwm pins. 11.9 i/o registers the following i/o registers control and monitor operation of the tim: tima status and cont rol register (tasc) tima control regist ers (tacnth:tacntl) tima counter modulo regi sters (tamodh:tamodl) tima channel status and contro l registers (t asc0 and tasc1) tima channel register s (tach0h:tach0l and tach1h:tach1l) 1 bus frequency ------------------- ------------------ t su + timer interface module a (tima) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module a (tima) 215 non-disclosure agreement required 11.9.1 tima status and control register the tima status and control r egister does the following: enables tima overflow interrupts flags tima overflows stops the tima counter resets the tima counter prescales the tima counter clock tof ? tima overflow flag bit this read/write flag is set when the tima counter resets to $0000 after reaching the modulo value program med in the tima counter modulo registers. clear tof by reading the tima status and control register when tof is set and then writing a logic 0 to tof. if another tima overflow occurs before the clear ing sequence is complete, then writing logic 0 to tof has no ef fect. therefore, a tof interrupt request cannot be lost du e to inadvertent clea ring of tof. reset clears the tof bit. writing a logic 1 to tof has no effect. 1 = tima counter ha s reached modulo value 0 = tima counter has not reached modulo value toie ? tima overflow interrupt enable bit this read/write bit enables tima overflow interr upts when the tof bit becomes set. reset cl ears the toie bit. 1 = tima overflow interrupts enabled 0 = tima overflow interrupts disabled address: $000c bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0trst reset:00100000 = unimplemented figure 11-4. tima status and control register (tasc) non-disclosure agreement required timer interface module a (tima) technical data MC68HC708MP16 ? rev. 3.1 216 timer interface module a (tima) freescale semiconductor tstop ? tima stop bit this read/write bit stop s the tima counter. counting resumes when tstop is cleared. reset sets t he tstop bit, stopping the tima counter until software clears the tstop bit. 1 = tima counter stopped 0 = tima counter active note: do not set the tstop bit before enter ing wait mode if the tima is required to exit wait mode. trst ? tima reset bit setting this write-only bit resets the tima counte r and the tima prescaler. setting trst has no ef fect on any other registers. counting resumes from $0000 . trst is cleared automatically after the tima counter is re set and always reads as logic 0. reset clears the trst bit. 1 = prescaler and tima counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tima counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select either the pte0/tclka pin or one of the seven prescaler outputs as the input to the tima counter as table 11-1 shows. reset clear s the ps[2:0] bits. table 11-1. prescaler selection ps[2:0] tima clock source 000 internal bus clock 1 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 pte0/tclka timer interface module a (tima) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module a (tima) 217 non-disclosure agreement required 11.9.2 tima counter registers the two read-only tima counter regist ers contain the high and low bytes of the value in the tima counter . reading the high byte (tacnth) latches the contents of the low byte (tacntl) into a buffer. subsequent reads of tacnth do not affect the latched tacntl value until tacntl is read. reset clears the tima counter registers. setting the tima reset bit (trst) also clears t he tima counter registers. note: if you read tacnth during a break in terrupt, be sure to unlatch tacntl by reading tacntl before exiting the break interrupt. otherwise, tacntl retains the value latched during the break. tac n t h $000d bit 7 654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 tacntl $000ebit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 = unimplemented figure 11-5. tima counter register s (tacnth:tacntl) non-disclosure agreement required timer interface module a (tima) technical data MC68HC708MP16 ? rev. 3.1 218 timer interface module a (tima) freescale semiconductor 11.9.3 tima counter modulo registers the read/write tima modulo registers contain the modulo value for the tima counter. when the tima counter reaches the m odulo value, the overflow flag (tof) bec omes set, an d the tima counter resumes counting from $0000 at the next cl ock. writing to the high byte (tamodh) inhibits the to f bit and overflow interr upts until the low byte (tamodl) is written. reset sets the tima counter modulo registers. note: reset the tima counter before wr iting to the tima counter modulo registers. ta m o d h $000f bit 7 654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 ta m o d l $0010 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 11-6. tima counter modulo registers (tamodh:tamodl) timer interface module a (tima) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module a (tima) 219 non-disclosure agreement required 11.9.4 tima channel status and control registers each of the tima channel status and control registers does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or t oggling output on output compare selects rising edge, fall ing edge, or any edge as the active input capture trigger selects output toggl ing on tima overflow selects 100% pwm duty cycle selects buffered or unbuffer ed output compare/pwm operation tasc0 $0011bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 tasc1 $0014bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 11-7. tima channel st atus and control registers (tasc0:tasc1) non-disclosure agreement required timer interface module a (tima) technical data MC68HC708MP16 ? rev. 3.1 220 timer interface module a (tima) freescale semiconductor chxf ? chann el x flag bit when channel x is an inpu t capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tima counter registers matche s the value in the ti ma channel x registers. when tima cpu interrupt requests are enabled (chxie=1), clear chxf by reading the tima channel x status and co ntrol register with chxf set and then writ ing a logic 0 to chxf . if another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to chxf has no effect. ther efore, an interr upt request cannot be lost due to inadver tent clearing of chxf. reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or out put compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x in terrupt enable bit this read/write bi t enables tima cpu interr upt service requests on channel x. reset cl ears the chxie bit. 1 = channel x cpu inte rrupt requests enabled 0 = channel x cpu interr upt requests disabled msxb ? mode select bit b this read/write bit sele cts buffered output co mpare/pwm operation. msxb exists only in the tima channe l 0 status and control register. setting ms0b disables the channel 1 status and control register and reverts tch1 to gen eral-purpose i/o. reset clears the msxb bit. 1 = buffered output com pare/pwm operation enabled 0 = buffered output compar e/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit se lects either input capture operation or unbuffered outp ut compare/pwm operation. see table 11-2 . 1 = unbuffered output compare/pwm operation 0 = input capt ure operation timer interface module a (tima) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module a (tima) 221 non-disclosure agreement required when elsxb:a = 00, this read/write bit selects the in itial output level of the tchx pin. (see table 11-2 .). reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bi ts in the tima status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an i nput capture channel, th ese read/write bits control the active edge- sensing logic on channel x. when channel x is an output co mpare channel, elsxb and elsxa control the channel x output beh avior when an output compare occurs. when elsxb and elsxa are both cl ear, channel x is not connected to port e, and pin ptex /tchxa is available as a general-purpose i/o pin. table 11-2 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. table 11-2. mode, edge, and level selection msxb:msxa elsxb:elsxa mode configuration x0 00 output preset pin under port control; initial output level high x1 00 pin under port control; initial output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 01 output compare or pwm toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare non-disclosure agreement required timer interface module a (tima) technical data MC68HC708MP16 ? rev. 3.1 222 timer interface module a (tima) freescale semiconductor note: before enabling a tima channel register for input capture operation, make sure that t he ptex/tachx pin is stable for at least two bus clocks. tovx ? toggle-on-overflow bit when channel x is an output compar e channel, this read/write bit controls the behavior of the channel x output when the tima counter overflows. when channel x is an i nput capture channel, tovx has no effect. reset clear s the tovx bit. 1 = channel x pin toggles on tima counter overflow. 0 = channel x pin does not toggl e on tima counter overflow. note: when tovx is set, a tima counter overflow takes precedence over a channel x output compare if bot h occur at the same time. chxmax ? channel x ma ximum duty cycle bit when the tovx bit is at logic 0, setting the chxmax bit forces the duty cycle of buffered and unbuffe red pwm signals to 100%. as figure 11-8 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 11-8. chxmax latency output overflow ptex/tachx period chxmax overflow overflow overflow overflow compare output compare output compare output compare timer interface module a (tima) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module a (tima) 223 non-disclosure agreement required 11.9.5 tima channel registers these read/write registers contain t he captured tima c ounter value of the input capture functi on or the output compar e value of the output compare function. the stat e of the tima channel registers after reset is unknown. in input capture mode (m sxb:msxa = 0:0), reading the high byte of the tima channel x registers (tachxh) inhibits input captures until the low byte (tachxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tima channel x regist ers (tachxh) inhibits output compares until the low byte (tachxl) is written. tach0h $0012bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset tach0l $0013bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset tach1h $0015bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset tac h 1 l $0016bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset figure 11-9. tima channel r egisters (tach0h/l:tach1h/l) non-disclosure agreement required timer interface module a (tima) technical data MC68HC708MP16 ? rev. 3.1 224 timer interface module a (tima) freescale semiconductor MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module b (timb) 225 non-disclosure agreement required technical data ? MC68HC708MP16 section 12. timer interface module b (timb) 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 12.4.1 timb counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . 230 12.4.2 input capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 12.4.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 12.4.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 230 12.4.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .231 12.4.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . 232 12.4.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 233 12.4.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 234 12.4.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 12.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 12.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 12.7 timb during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . . 238 12.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 12.8.1 timb clock pin (pte3/ tclkb). . . . . . . . . . . . . . . . . . . . . 238 12.8.2 timb channel i/o pins (pte 4/tch0b:pte7/tch3b) . . . 239 12.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 12.9.1 timb status and cont rol register. . . . . . . . . . . . . . . . . . . 240 12.9.2 timb counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . 242 12.9.3 timb counter modulo registers . . . . . . . . . . . . . . . . . . . .243 12.9.4 timb channel status and control registers . . . . . . . . . . 244 12.9.5 timb channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . 248 non-disclosure agreement required timer interface module b (timb) technical data MC68HC708MP16 ? rev. 3.1 226 timer interface module b (timb) freescale semiconductor 12.2 introduction this section describes the timer inte rface module (tim4, version b). the timb is a four-channel timer that pr ovides a timing reference with input capture, output compare, and pul se-width-modulation functions. figure 12-1 is a block diagram of the timb. 12.3 features features of t he timb include: four input capture/out put compare channels ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable timb clock input ? seven-frequency internal bus clock prescaler selection ? external timb clock inpu t (4-mhz maximum frequency) free-running or modul o up-count operation toggle any channel pin on overflow timb counter stop and reset bits modular architecture expandable to eight channels 12.4 functional description figure 12-1 shows the structure of the timb. the central component of the timb is the 16-bit timb counte r that can operat e as a free-running counter or a modulo up-c ounter. the timb counter provides the timing reference for the input capture and output compare functions. the timb counter modulo registers, tbmodh:t bmodl, control the modulo value of the timb counter. software can re ad the timb counter value at any time without affectin g the counting sequence. the four timb channels are progr ammable independently as input capture or output compare channels. timer interface module b (timb) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module b (timb) 227 non-disclosure agreement required figure 12-1. timb block diagram prescaler prescaler select tclk internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tbch0h:tbch0l ms0a els0b els0a pte4 tof toie inter- 16-bit comparator 16-bit latch tbch1h:tbch1l 16-bit comparator 16-bit latch tbch2h:tbch2l 16-bit comparator 16-bit latch tbch3h:tbch3l channel 0 channel 1 channel 2 channel 3 tbmodh:tbmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f els2b els2a tov2 ch2ie ch2max ch2f els3b els3a tov3 ch3ie ch3max ch3f ch0max ms0b ms2b 16-bit counter internal bus bus clock ms1a ms2a ms3a pte3/tclkb pte4/tch0b pte5/tch1b pte6/tch2b pte7/tch3b logic rupt logic inter- rupt logic pte5 logic inter- rupt logic pte6 logic inter- rupt logic pte7 logic inter- rupt logic non-disclosure agreement required timer interface module b (timb) technical data MC68HC708MP16 ? rev. 3.1 228 timer interface module b (timb) freescale semiconductor addr. name bit 7 6 5 4 3 2 1 bit 0 $003f timer b status and control register (tbsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 0 0 0 0 0 0 0 0 $0040 timer b counter register high (tbcnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0041 timer b counter register low (tbcntl) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0042 timer b modulo register high (tbmodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0043 timer b modulo register low (tbmodl) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0044 timer b channel 0 status and control register (tbsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 $0045 timer b channel 0 register high (tbch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0046 timer b channel 0 register low (tbch0l) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0047 timer b channel 1 status and control register (tbsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 0 0 0 0 0 0 0 0 = unimplemented figure 12-2. timb i/ o register summary timer interface module b (timb) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module b (timb) 229 non-disclosure agreement required $0048 timer b channel 1 register high (tbch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0049 timer b channel 1 register low (tbch1l) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $004a timer b channel 2 status and control register (tbsc2) read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 0 0 0 0 0 0 0 0 $004b timer b channel 2 register high (tbch2h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $004c timer b channel 2 register low (tbch2l) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $004d timer b channel 3 status and control register (tbsc3) read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset: 0 0 0 0 0 0 0 0 $004e timer b channel 3 register high (tbch3h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $004f timer b channel 3 register low (tbch3l) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset addr. name bit 7 6 5 4 3 2 1 bit 0 = unimplemented figure 12-2. timb i/ o register summary non-disclosure agreement required timer interface module b (timb) technical data MC68HC708MP16 ? rev. 3.1 230 timer interface module b (timb) freescale semiconductor 12.4.1 timb counter prescaler the timb clock source can be one of the seven prescaler outputs or the timb clock pin, pte3/tclkb. the prescaler generat es seven clock rates from the internal bus clock. the prescaler se lect bits, ps[2:0], in the timb status and co ntrol register select the timb clock source. 12.4.2 input capture with the input capture function, the timb can capture th e time at which an external event occurs . when an active edge o ccurs on the pin of an input capture channel, the timb la tches the contents of the timb counter into the timb channel regi sters, tbchxh:tbchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 12.4.3 output compare with the output compare function, the timb can generate a periodic pulse with a progr ammable polarity, duration, and frequency. when the counter reaches the value in the r egisters of an output compare channel, the timb can se t, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. 12.4.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 12.4.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the ol d value currently in th e timb channel registers. an unsynchronized write to the timb channel registers to change an output compare value could cause incorrect operati on for up to two counter overflow periods. for exampl e, writing a new value before the counter reaches the old value but after the c ounter reaches the new value prevents any compare during that counter overflow period. also, using a timb overflow interrupt rout ine to write a new , smaller output timer interface module b (timb) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module b (timb) 231 non-disclosure agreement required compare value may caus e the compare to be missed. the timb may pass the new value bef ore it is written. use the following methods to synch ronize unbuffered changes in the output compare va lue on channel x: when changing to a smaller va lue, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse . the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare val ue, enable channel x timb overflow inte rrupts and write the new value in the timb overflow interrupt routine. the timb overflow interrupt occurs at the end of the cu rrent counter overflow per iod. writing a larger value in an output co mpare interrupt routin e (at the end of the current pulse) could c ause two output compar es to occur in the same counter overflow period. 12.4.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appe ars on the pte4/tch0 b pin. the timb channel registers of th e linked pair alternatel y control the output. setting the ms0b bit in timb channe l 0 status and control register (tbsc0) links channel 0 and channel 1. the output compare value in the timb channel 0 regist ers initially controls the output on the pte4/tch0b pin. writing to the timb channel 1 registers enables the timb channel 1 registers to synchr onously control the output after the timb overflows. at each subseque nt overflow, the timb channel registers (0 or 1) that control the output are t he ones written to last. tbsc0 controls and monitors the buf fered output compar e function, and timb channel 1 status and control regi ster (tbsc1) is unused. while the ms0b bit is set, the channel 1 pin, pte5/tch1b, is available as a general-purpose i/o pin. non-disclosure agreement required timer interface module b (timb) technical data MC68HC708MP16 ? rev. 3.1 232 timer interface module b (timb) freescale semiconductor channels 2 and 3 can be linked to form a buffered output compare channel whose output appe ars on the pte6/tch2 b pin. the timb channel registers of th e linked pair alternatel y control the output. setting the ms2b bit in timb channe l 2 status and control register (tbsc2) links channel 2 and channel 3. the output compare value in the timb channel 2 regist ers initially controls the output on the pte6/tch2b pin. writing to the timb channel 3 registers enables the timb channel 3 registers to synchr onously control the output after the timb overflows. at each subseque nt overflow, the timb channel registers (2 or 3) that control the output are t he ones written to last. tbsc2 controls and monitors the buf fered output compar e function, and timb channel 3 status and control regi ster (tbsc3) is unused. while the ms2b bit is set, the channel 3 pin, pte7/tch3b, is available as a general-purpose i/o pin. note: in buffered output compare operati on, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares. 12.4.4 pulse width modulation (pwm) by using the toggle-on-overflow f eature with an output compare channel, the timb can generate a pwm signal. the value in the timb counter modulo registers determi nes the period of th e pwm signal. the channel pin toggles when the counter reaches the value in the timb counter modulo registers. the time between ov erflows is the period of the pwm signal. as figure 12-3 shows, the output compare value in the timb channel registers determines t he pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the timb to clear the channel pin on output compare if the state of the pwm pulse is logic 1. program the timb to set the pin if the state of the pwm pulse is logic 0. timer interface module b (timb) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module b (timb) 233 non-disclosure agreement required figure 12-3. pwm peri od and pulse width the value in the timb counter m odulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is va riable in 256 in crements. writing $00ff (255) to the timb counter modulo regi sters produces a pwm period of 256 times the in ternal bus clock period if the prescaler select value is $000 (see 12.9.1 timb status a nd control register ). the value in the timb channel regist ers determines the pulse width of the pwm output. the puls e width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the timb channel registers produces a duty cycl e of 128/256 or 50%. 12.4.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 12.4.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currentl y in the timb channel registers. an unsynchronized write to the timb channel registers to change a pulse width value coul d cause incorrect operat ion for up to two pwm periods. for example, writing a ne w value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a ti mb overflow interrupt ptex/tchxb period pulse width overflow overflow overflow output compare output compare output compare non-disclosure agreement required timer interface module b (timb) technical data MC68HC708MP16 ? rev. 3.1 234 timer interface module b (timb) freescale semiconductor routine to write a new, smaller pulse width val ue can cause the compare to be missed. the timb may pass the new valu e before it is written. use the following methods to synch ronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pu lse. the interrupt routi ne has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable channel x timb overflow interrupts and write the new value in the timb overflow interrupt routine. the timb overflow interrupt occurs at the end of the current pwm period. writin g a larger value in an output compare interrupt routine (at t he end of the curr ent pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 12.4.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the pte4 /tch0b pin. the timb channel registers of the linked pair alternately contro l the pulse width of the output. setting the ms0b bit in timb channe l 0 status and control register (tbsc0) links channel 0 and channel 1. the timb channel 0 registers initially control the pulse width on the pte4/tch0b pin. writing to the timb channel 1 regist ers enables the timb channel 1 regi sters to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the timb channel registers (0 or 1) that control the pul se width are the ones written to last. tbsc0 controls and monitors the buffer ed pwm function, and timb channel 1 timer interface module b (timb) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module b (timb) 235 non-disclosure agreement required status and control register (tbsc1) is unused. while the ms0b bit is set, the channel 1 pin, pte5/tch1b, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered pwm channel whose output appears on the pte6 /tch2b pin. the timb channel registers of the linked pair alternately contro l the pulse width of the output. setting the ms2b bit in timb channe l 2 status and control register (tbsc2) links channel 2 and channel 3. the timb channel 2 registers initially control the pulse width on the pte6/tch2b pin. writing to the timb channel 3 regist ers enables the timb channel 3 regi sters to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the timb channel registers (2 or 3) that control the pul se width are the ones written to last. tbsc2 controls and monitors the buffer ed pwm function, and timb channel 3 status and control register (tbsc3) is unused. while the ms2b bit is set, the channel 3 pin, pte7/tch3b, is available as a general-purpose i/o pin. note: in buffered pwm signal gener ation, do not write new pulse width values to the currently active channel registers. writi ng to the acti ve channel registers is the same as gen erating unbuffe red pwm signals. 12.4.4.3 pwm initialization to ensure correct operation when gen erating unbuffered or buffered pwm signals, use the follow ing initializat ion procedure: 1. in the timb status and control register (tbsc): a. stop the timb counter by sett ing the timb stop bit, tstop. b. reset the timb counter by sett ing the timb re set bit, trst. 2. in the timb counter modulo r egisters (tbmodh:tbmodl), write the value for the required pwm period. 3. in the timb channel x registers (tbchxh :tbchxl), write the value for the requ ired pulse width. non-disclosure agreement required timer interface module b (timb) technical data MC68HC708MP16 ? rev. 3.1 236 timer interface module b (timb) freescale semiconductor 4. in timb channel x status and contro l register (tbscx): a. write 0:1 (for unbuffered outp ut compare or pwm signals) or 1:0 (for buffered outp ut compare or pwm si gnals) to the mode select bits, msxb:msxa. (see table 12-2 .) b. write 1 to the toggle- on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level se lect bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 12-2 .) note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the timb stat us control register (tbsc) , clear the ti mb stop bit, tstop. setting ms0b links chann els 0 and 1 and configur es them for buffered pwm operation. the timb channel 0 registers (tbch0h:tbch0l) initially control the buff ered pwm output. timb st atus control register 0 (tbscr0) controls and monitors t he pwm signal fr om the linked channels. ms0b takes pr iority over ms0a. setting ms2b links chann els 2 and 3 and configur es them for buffered pwm operation. the timb channel 2 registers (tbch2h:tbch2l) initially control the pwm output. ti mb status cont rol register 2 (tbscr2) controls and monitors t he pwm signal fr om the linked channels. ms2b takes pr iority over ms2a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on timb overflows. subsequen t output compares try to force the output to a state it is already in and have no effect. the resu lt is a 0% duty cycle output. timer interface module b (timb) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module b (timb) 237 non-disclosure agreement required setting the channel x maximum dut y cycle bit (chxm ax) and clearing the tovx bit generates a 100% duty cycle output. (see 12.9.4 timb channel status and c ontrol registers .) 12.5 interrupts the following timb sources can generate interrupt requests: timb overflow flag (tof) ? the to f bit is set when the timb counter value rolls over to $0000 after matching t he value in the timb counter modulo registers. the timb overflow interrupt enable bit, toie, enables timb overflow cpu interrupt requests. tof and toie are in the timb status a nd control register. timb channel flags (ch3f?ch0f) ? the chxf bit is set when an input capture or output compar e occurs on channel x. channel x tim cpu interrupt requests ar e controlled by the channel x interrupt enable bit, chxie. c hannel x tim cpu interrupt requests are enabled when chxie= 1. chxf and chxie are in the timb channel x status and control register. 12.6 wait mode the wait instruction puts the mcu in low-power-consumption standby mode. the timb remains active af ter the execution of a wait instruction. in wait mode the timb registers ar e not accessible by the cpu. any enabled cpu interrupt reque st from the timb can bring the mcu out of wait mode. if timb functions are not requir ed during wait mode, reduce power consumption by stoppi ng the timb before ex ecuting the wait instruction. non-disclosure agreement required timer interface module b (timb) technical data MC68HC708MP16 ? rev. 3.1 238 timer interface module b (timb) freescale semiconductor 12.7 timb during break interrupts a break interrupt stops the timb counter. the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during t he break state. (see 7.7.4 sim break flag control register .) to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect status bits du ring the break state, writ e a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), software can read and write i/o registers during the break state wi thout affecting status bits. some status bits have a two-step read/wr ite clearing proce dure. if software does the first step on su ch a bit before the br eak, the bit cannot change during the break state as long as bcf e is at logic 0. after the break, doing the second step cl ears the status bit. 12.8 i/o signals port e shares five of its pins with the tim. pte3/tcl kb is an external clock input to the timb prescaler. the four timb channel i/o pins are pte4/tch0b, pte5/tch1b, pte6/tch2b, and pte7/tch3b. 12.8.1 timb clock pin (pte3/tclkb) pte3/tclkb is an external clock inpu t that can be the clock source for the timb counter instead of the presca led internal bus clock. select the pte3/tclkb input by writ ing logic 1s to the thr ee prescaler select bits, ps[2:0]. (see 12.9.1 timb status and control register .) timer interface module b (timb) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module b (timb) 239 non-disclosure agreement required the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is: bus frequency 2 pte3/tclkb is avail able as a general-purpose i/o pin when not used as the timb clock input . when the pte3/tclkb pi n is the timb clock input, it is an input regardless of the state of the ddre3 bit in data direction register e. 12.8.2 timb channel i/o pins (pte4/tch0b:pte7/tch3b) each channel i/o pin is progr ammable independently as an input capture pin or an output compare pin. pte4/tch0b and pte6/tch2b can be configured as buffered output compare or buffered pwm pins. 12.9 i/o registers the following i/o registers control and monitor operation of the timb: timb status and cont rol register (tbsc) timb control regist ers (tbcnth:tbcntl) timb counter modulo regi sters (tbmodh:tbmodl) timb channel status and contro l registers (tbsc0, tbsc1, tbsc2, and tbsc3) timb channel registers (tb ch0h:tbch0l, tbch1h:tbch1l, tbch2h:tbch2l, and tbch3h:tbch3l) 1 bus frequency ------------------- ------------------ t su + non-disclosure agreement required timer interface module b (timb) technical data MC68HC708MP16 ? rev. 3.1 240 timer interface module b (timb) freescale semiconductor 12.9.1 timb status and control register the timb status and control r egister does the following: enables timb overflow interrupts flags timb overflows stops the timb counter resets the timb counter prescales the timb counter clock tof ? timb overflow flag bit this read/write flag is set when the timb counter resets to $0000 after reaching the modulo value program med in the timb counter modulo registers. clear tof by reading the timb status and control register when tof is set and then writing a logic 0 to tof. if another timb overflow occurs before the clear ing sequence is complete, then writing logic 0 to tof has no ef fect. therefore, a tof interrupt request cannot be lost du e to inadvertent clea ring of tof. reset clears the tof bit. writing a logic 1 to tof has no effect. 1 = timb counter ha s reached modulo value 0 = timb counter has not reached modulo value toie ? timb overflow interrupt enable bit this read/write bit enables timb overflow interr upts when the tof bit becomes set. reset cl ears the toie bit. 1 = timb overflow interrupts enabled 0 = timb overflow interrupts disabled address: $003f bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0trst reset:00100000 = unimplemented figure 12-4. timb status and control register (tbsc) timer interface module b (timb) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module b (timb) 241 non-disclosure agreement required tstop ? timb stop bit this read/write bit stop s the timb counter. counting resumes when tstop is cleared. reset sets t he tstop bit, stopping the timb counter until software clears the tstop bit. 1 = timb counter stopped 0 = timb counter active note: do not set the tstop bit before enter ing wait mode if the timb is required to exit wait mode. trst ? timb reset bit setting this write-only bit resets the timb counte r and the timb prescaler. setting trst has no ef fect on any other registers. counting resumes from $0000 . trst is cleared automatically after the timb counter is re set and always reads as logic 0. reset clears the trst bit. 1 = prescaler and timb counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the timb counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select either the pte3/tclkb pin or one of the seven prescaler outputs as the input to the timb counter as table 12-1 shows. reset clear s the ps[2:0] bits. table 12-1. pres caler selection ps[2:0] timb clock source 000 internal bus clock 1 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 pte3/tclkb non-disclosure agreement required timer interface module b (timb) technical data MC68HC708MP16 ? rev. 3.1 242 timer interface module b (timb) freescale semiconductor 12.9.2 timb counter registers the two read-only timb counter regist ers contain the high and low bytes of the value in the timb counter . reading the high byte (tbcnth) latches the contents of the low byte (tbcntl) into a buffer. subsequent reads of tbcnth do not affect the latched tbcntl value until tbcntl is read. reset clears the timb counter registers. setting the timb reset bit (trst) also clears t he timb counter registers. note: if you read tbcnth during a break in terrupt, be sure to unlatch tbcntl by reading tbcntl before exiting the break interrupt. otherwise, tbcntl retains the value latched during the break. tbcnth $0040 bit 7 654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 tbcntl $0041 bit 7 654321bit 0 read: bit 7654321bit 0 write: reset:00000000 = unimplemented figure 12-5. timb counter registers (tbcnth:tbcntl) timer interface module b (timb) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module b (timb) 243 non-disclosure agreement required 12.9.3 timb counter modulo registers the read/write timb modulo registers contain the modulo value for the timb counter. when the timb counter reaches the m odulo value, the overflow flag (tof) bec omes set, an d the timb counter resumes counting from $0000 at the next cl ock. writing to the high byte (tbmodh) inhibits the to f bit and overflow interr upts until the low byte (tbmodl) is written. reset sets the timb counter modulo registers. note: reset the timb counter before wr iting to the timb counter modulo registers. tbmodh $0042bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 tbmodl $0043 bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 12-6. timb counter modul o registers (tbmodh:tbmodl) non-disclosure agreement required timer interface module b (timb) technical data MC68HC708MP16 ? rev. 3.1 244 timer interface module b (timb) freescale semiconductor 12.9.4 timb channel status and control registers each of the timb channel status and control registers does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or t oggling output on output compare selects rising edge, fall ing edge, or any edge as the active input capture trigger selects output toggl ing on timb overflow selects 100% pwm duty cycle selects buffered or unbuffer ed output compare/pwm operation tbsc0 $0044 bit 7 6 5 4 3 2 1 bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 tbsc1 $0047 bit 7 6 5 4 3 2 1 bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 tbsc2 $004a bit 7 6 5 4 3 2 1 bit 0 read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 tbsc3 $004d bit 7 6 5 4 3 2 1 bit 0 read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset:00000000 = unimplemented figure 12-7. timb channel status and control registers (tbsc0:tbsc3) timer interface module b (timb) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module b (timb) 245 non-disclosure agreement required chxf ? chann el x flag bit when channel x is an inpu t capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the timb counter registers matche s the value in the ti mb channel x registers. when tim cpu interrupt requests ar e enabled (chxie = 1), clear chxf by reading timb channel x status an d control register with chxf set and then writ ing a logic 0 to chxf . if another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to chxf has no effect. ther efore, an interr upt request cannot be lost due to inadver tent clearing of chxf. reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or out put compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x in terrupt enable bit this read/write bit enabl es timb cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu inte rrupt requests enabled 0 = channel x cpu interr upt requests disabled msxb ? mode select bit b this read/write bit sele cts buffered output co mpare/pwm operation. msxb exists only in the timb c hannel 0 and timb ch annel 2 status and control registers. setting ms0b disables the channel 1 status and control register and reverts tch1b to general-purpose i/o. setting ms2b disables the channel 3 status and control register and reverts tch3b to general-purpose i/o. reset clears the msxb bit. 1 = buffered output com pare/pwm operation enabled 0 = buffered output compar e/pwm operation disabled non-disclosure agreement required timer interface module b (timb) technical data MC68HC708MP16 ? rev. 3.1 246 timer interface module b (timb) freescale semiconductor msxa ? mode select bit a when elsxb:a 00, this read/write bit se lects either input capture operation or unbuffered output co mpare/pwm oper ation. (see table 12-2 .) 1 = unbuffered output compare/pwm operation 0 = input capt ure operation when elsxb:a = 00, this read/write bit selects the in itial output level of the tchxb pin. (see table 12-2 .) reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bi ts in the timb status and control register (tbsc). elsxb and elsxa ? edge/level select bits when channel x is an i nput capture channel, th ese read/write bits control the active edge- sensing logic on channel x. when channel x is an output co mpare channel, elsxb and elsxa control the channel x output beh avior when an output compare occurs. when elsxb and elsxa are both cl ear, channel x is not connected to port e, and pin ptex /tchxb is available as a general-purpose i/o pin. table 12-2 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. note: before enabling a timb channel register for input capture operation, make sure that t he pte/tchxb pin is stable fo r at least two bus clocks. timer interface module b (timb) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module b (timb) 247 non-disclosure agreement required tovx ? toggle-on-overflow bit when channel x is an output compar e channel, this read/write bit controls the behavior of the channel x output when the timb counter overflows. when channel x is an i nput capture channel, tovx has no effect. reset clear s the tovx bit. 1 = channel x pin toggles on timb counter overflow. 0 = channel x pin does not toggl e on timb counter overflow. note: when tovx is set, a timb counter overflow takes precedence over a channel x output compare if bot h occur at the same time. chxmax ? channel x ma ximum duty cycle bit when the tovx bit is at logic 0, setting the chxmax bit forces the duty cycle of buffered and unbuffe red pwm signals to 100%. as figure 12-8 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. table 12-2. mode, edge, and level selection msxb:msxa elsxb:elsxa mode configuration x0 00 output preset pin under port control; initial output level high x1 00 pin under port control; initial output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 01 output compare or pwm toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare non-disclosure agreement required timer interface module b (timb) technical data MC68HC708MP16 ? rev. 3.1 248 timer interface module b (timb) freescale semiconductor figure 12-8. chxmax latency 12.9.5 timb channel registers these read/write registers contain t he captured timb c ounter value of the input capture functi on or the output compar e value of the output compare function. the stat e of the timb channel registers after reset is unknown. in input capture mode (m sxb:msxa = 0:0), reading the high byte of the timb channel x registers (tbchxh) inhibits input captures until the low byte (tbchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the timb channel x regist ers (tbchxh) inhibits output compares until the low byte (tbchxl) is written. output overflow ptex/tchxb period chxmax overflow overflow overflow overflow compare output compare output compare output compare tbch0h $0045bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset tbch0l $0046bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 12-9. timb channel registers (tbch0h/l:tbch3h/l) timer interface module b (timb) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor timer interface module b (timb) 249 non-disclosure agreement required tbch1h $0048bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset tbch1l $0049bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset tbch2h $004bbit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset tbch2l $004c bit 7 654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset tbch3h $004ebit 7654321bit 0 reset: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset tbch3l $004f bit 7 654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 12-9. timb channel registers (tbch0h/l:tbch3h/l) (continued) non-disclosure agreement required timer interface module b (timb) technical data MC68HC708MP16 ? rev. 3.1 250 timer interface module b (timb) freescale semiconductor MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial peripheral interface module (spi) 251 non-disclosure agreement required technical data ? MC68HC708MP16 section 13. serial peripheral interface module (spi) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 13.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 13.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 13.5.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 13.5.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 13.6 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 13.6.1 clock phase and polarity controls . . . . . . . . . . . . . . . . . . 258 13.6.2 transmission format wh en cpha = 0 . . . . . . . . . . . . . . . 258 13.6.3 transmission format when cpha = 1 . . . . . . . . . . . . . . . 260 13.6.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . 261 13.7 queuing transmissi on data . . . . . . . . . . . . . . . . . . . . . . . . . . 263 13.8 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 13.8.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 13.8.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 13.9 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 13.10 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 13.11 low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 13.12 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 272 13.13 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 13.13.1 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . .273 13.13.2 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . .274 13.13.3 spsck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 13.13.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 13.13.5 cgnd (clock ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 non-disclosure agreement required serial peripheral interface module (spi) technical data MC68HC708MP16 ? rev. 3.1 252 serial peripheral interface module (spi) freescale semiconductor 13.14 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 13.14.1 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 13.14.2 spi status and control register . . . . . . . . . . . . . . . . . . . .279 13.14.3 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 13.2 introduction the spi allows full-duplex, synchron ous, serial communications with peripheral devices. 13.3 features features of the spi modu le include the following: full-duplex operation master and slave modes double-buffered operation with separate transmit and receive registers four master mode frequencie s (maximum = bus frequency 2) maximum slave mode frequency = bus frequency clock ground for reduced radio frequency (rf) interference serial clock with program mable polarity and phase two separately enabled inte rrupts with cpu service: ? sprf (spi receiver full) ? spte (spi transmitter empty) mode fault error flag wi th cpu interrupt capability overflow error flag with cpu interrupt capability programmable wired-or mode i 2 c (inter-integrated ci rcuit) compatibility serial peripheral interface module (spi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial peripheral interface module (spi) 253 non-disclosure agreement required 13.4 pin name conventions the generic names of th e spi i/o pins are: ss (slave select) spsck (spi serial clock) cgnd (clock ground) mosi (master out slave in) miso (master in slave out) spi pins are shared by par allel i/o ports or have alternate functions. the full name of an spi pin re flects the name of the shared port pin or the name of an alternate pin function. the generic pin names appear in the text that follows. table 13-1 shows the full names of the spi i/o pins. table 13-1. pin name conventions generic pin names: miso mosi spsck ss cgnd full pin names: pf3/miso pf2/mosi pf0/spsck pf1/ss cgnd/ev ss non-disclosure agreement required serial peripheral interface module (spi) technical data MC68HC708MP16 ? rev. 3.1 254 serial peripheral interface module (spi) freescale semiconductor 13.5 functional description figure 13-1 shows the structure of the spi module and figure 13-2 shows the locations and content s of the spi i/o registers. figure 13-1. spi module block diagram transmitter cpu interrupt request reserved receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 cgmout 3 2 clock select 2 clock divider 8 32 128 clock logic cpha cpol spi sprie dmas spe spwom sprf spte ovrf reserved m s pin control logic receive data register sptie spe internal bus (from sim) modfen errie control modf spmstr mosi miso spsck ss serial peripheral interface module (spi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial peripheral interface module (spi) 255 non-disclosure agreement required the spi module allows full-duplex, synchronous, serial communication between the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi opera tion can be interrupt- driven. all spi interrupts c an be serviced by the cpu. the following paragraphs describe the operation of the spi module. 13.5.1 master mode the spi operates in mast er mode when the spi ma ster bit, spmstr, is set. note: configure the spi modul es as master or sl ave before enab ling them. enable the master spi before enabling the slave spi. disable the slave spi before disabling t he master spi. (see 13.14.1 spi control register .) addr. name bit 7 6 5 4 3 2 1 bit 0 $001b spi control register (spcr) read: sprie dmas spmstr cpol cpha spwom spe sptie write: reset: 0 0 1 0 1 0 0 0 $001c spi status and control register (spscr) read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset: 0 0 0 0 1 0 0 0 $001d spi data register (spdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset = unimplemented figure 13-2. spi i/o register summary non-disclosure agreement required serial peripheral interface module (spi) technical data MC68HC708MP16 ? rev. 3.1 256 serial peripheral interface module (spi) freescale semiconductor only a master spi modul e can initiate transmi ssions. software begins the transmission from a master spi module by wr iting to t he transmit data register. if the shift register is empty, the by te immediately transfers to the shift register, setting the spi transmitter empty bit, spte. the byte begins shifting out on the mosi pin under the control of the serial clock. see figure 13-3 . the spr1 and spr0 bits control t he baud rate generator and determine the speed of the sh ift register. (see 13.14.2 spi stat us and control register .) through the spsck pin, the baud rate generator of the master also controls the shift register of the slave peripheral. as the byte shifts out on the mosi pin of the ma ster, another byte shifts in from the slave on the master?s miso pin. the transmission ends when the receiver full bit, sprf, becomes set. at t he same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, spr f signals the end of a transmission. software clears sprf by reading the sp i status and contro l register with sprf set and then r eading the spi data registe r. writing to the spi data register clears the spte bit. when the dmas bit is se t, the spi status and c ontrol register does not have to be read to clear the sprf bit. a read of the spi data register by the cpu clears t he sprf bit. a write to the spi data register by the cpu clears the spte bit. figure 13-3. full-duplex master-slave connections shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss serial peripheral interface module (spi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial peripheral interface module (spi) 257 non-disclosure agreement required 13.5.2 slave mode the spi operates in slave mode when t he spmstr bit is clear. in slave mode the spsck pin is the input for the serial clock from the master mcu. before a data tr ansmission occurs, the ss pin of the slave spi must be at logic 0. ss must remain low unti l the transmission is complete. (see 13.8.2 mode fault error .) in a slave spi module, dat a enters the shift regist er under the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it transfers to the re ceive data regi ster, and the sprf bit is set. to prevent an over flow condition, slave software then must read the receive da ta register before anothe r full byte enters the shift register. the maximum frequency of the spsck for an spi configur ed as a slave is the bus clock speed (which is twic e as fast as the fastest master spsck clock that can be generat ed). the frequency of the spsck for an spi configured as a slave does not have to correspond to any spi baud rate. the baud rate only cont rols the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. when the master spi starts a transm ission, the data in the slave shift register begins shifting out on the miso pin. the sl ave can load its shift register with a new byte for the next transmission by writin g to its transmit data register. the slave must write to its transmit data register at least one bus cycle before the master starts the next transmission. otherwise the byte already in the slave shift register shif ts out on the miso pin. data written to the slav e shift register during a transmission remains in a buffer until the end of the transmission. when the clock phase bit (cpha) is set, the first edge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. (see 13.6 transmission formats .) note: spsck must be in the pr oper idle state before the slave is enabled to prevent spsck from appearing as a clock edge. non-disclosure agreement required serial peripheral interface module (spi) technical data MC68HC708MP16 ? rev. 3.1 258 serial peripheral interface module (spi) freescale semiconductor 13.6 transmission formats during an spi transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock synchronizes shifting and sampling on the two seri al data lines. a slave select line allows selection of an i ndividual slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the slave select line can optional ly be used to i ndicate multiple- master bus contention. 13.6.1 clock phase and polarity controls software can select any of four co mbinations of seri al clock (spsck) phase and polarity using tw o bits in the spi cont rol register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no si gnificant effect on the transmission format. the clock phase (cpha) control bit se lects one of two fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase an d polarity are changed between transmissions to allow a master devic e to communicate with peripheral slaves having diff erent requirements. note: before writing to the cp ol bit or the cpha bi t, disable the spi by clearing the spi enable bit (spe) . 13.6.2 transmission format when cpha = 0 figure 13-4 shows an spi transmission in which cpha is logic 0. the figure should not be us ed as a replacement fo r data sheet parametric information.two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock ( spsck), master in/slave out (miso), and master out/slave in (m osi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line serial peripheral interface module (spi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial peripheral interface module (spi) 259 non-disclosure agreement required is the slave select input to the sl ave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconf igured as general-purpose i/o not af fecting the spi. (see 13.8.2 mode fault error .) when cpha = 0, the first spsck edge is the msb capture st robe. therefore the slav e must begin driving its data before the fi rst spsck edge, and a fa lling edge on the ss pin is used to start the slave dat a transmission. the slave?s ss pin must be toggled back to high and then low agai n between each byte transmitted as shown in figure 13-5 . figure 13-4. transmi ssion format (cpha = 0) figure 13-5. cpha/ss timing when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register . therefore, the spi data register of the slave bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # (for reference) spsck (cpol = 0) spsck (cpol =1) mosi (from master) miso (from slave) ss (to slave) capture strobe byte 1 byte 3 miso/mosi byte 2 master ss slave ss (cpha = 0) slave ss (cpha = 1) non-disclosure agreement required serial peripheral interface module (spi) technical data MC68HC708MP16 ? rev. 3.1 260 serial peripheral interface module (spi) freescale semiconductor must be loaded with transmit dat a before the falling edge of ss . any data written after the falling edge is stor ed in the transmit data register and transferred to the shift register after the current transmission. 13.6.3 transmission format when cpha = 1 figure 13-6 shows an spi transmission in which cpha is logic 1. the figure should not be us ed as a replacement fo r data sheet parametric information. two wave forms are shown for s psck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock ( spsck), master in/slave out (miso), and master out/slave in (m osi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the sl ave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconf igured as general-purpose i/o not af fecting the spi. (see 13.8.2 mode fault error .) when cpha = 1, the master begins driving its mosi pin on the first spsck edge. ther efore the slave uses the first spsck edge as a start transmission signal. the ss pin can remain low between transmissions. thi s format may be preferable in systems having only one master and only one slave driving the miso data line. figure 13-6. transmi ssion format (cpha = 1) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # (for reference) spsck (cpol = 0) spsck (cpol =1) mosi (from master) miso (from slave) ss (to slave) capture strobe serial peripheral interface module (spi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial peripheral interface module (spi) 261 non-disclosure agreement required when cpha = 1 for a slav e, the first edge of the spsck indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register . therefore, the spi data register of the slave must be loaded with transmit dat a before the first edge of spsck. any data written after the fi rst edge is stored in the transmit data register and transferred to the shift register after the current transmission. 13.6.4 transmission initiation latency when the spi is configured as a mast er (spmstr = 1), writing to the spdr starts a transmission . cpha has no ef fect on the delay to the start of the transmission, but it does affect the init ial state of the spsck signal. when cpha = 0, the spsck signal remains inactive for the first half of the first spsck cycle. when cpha = 1, the first spsck cycle begins with an edge on the spsck line from its inactive to its active level. the spi clock rate (selected by spr1:spr0) af fects the delay from the write to spd r and the start of t he spi transmission. (see figure 13-7 .) the internal spi clock in the master is a free-running derivative of the internal mcu clock. to conserve powe r, it is enabled only when both t he spe and spmstr bits are set. spsck edges occur halfway through the low time of the internal mcu cloc k. since the spi clock is free-running, it is uncertain where the write to the spdr occurs relative to the slower spsck. this uncertainty c auses the variation in the initiation delay shown in figure 13-7 . this delay is no longer than a single spi bit time. that is, the maximum delay is two mcu bus cycles for div2, eight mcu bus cycles for div8, 32 mcu bus cycles for div32, and 128 mcu bus cycl es for div128. non-disclosure agreement required serial peripheral interface module (spi) technical data MC68HC708MP16 ? rev. 3.1 262 serial peripheral interface module (spi) freescale semiconductor figure 13-7. transmissi on start delay (master) write to spdr initiation delay bus mosi spsck (cpha = 1) spsck (cpha = 0) spsck cycle number msb bit 6 12 clock write to spdr earliest latest (spsck = internal clock 2; earliest latest 2 possible start points) (spsck = internal clock 8; 8 possible start points) earliest latest (spsck = internal clock 32; 32 possible start points) earliest latest (spsck = internal clock 128; 128 possible start points) write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock ? ? ? initiation delay from write spdr to transfer begin serial peripheral interface module (spi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial peripheral interface module (spi) 263 non-disclosure agreement required 13.7 queuing transmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. the sp i transmitter empty flag (spte) indicates when the transmit data buffer is ready to acce pt new data. write to the transmit data register only when the spte bit is high. figure 13-8 shows the timing associated with doi ng back-to-back transmi ssions with the spi (spsck has cpha: cpol = 1:0). figure 13-8. sprf/spte cpu interrupt timing the transmit data buffer allows back- to-back transmissions without the slave precisely timing its writes between transmissions as in a system with a single data buffer. also, if no new data is wr itten to the data buffer, the last value contained in the shift register is the next data word to be transmitted. bit 3 mosi spsck spte write to spdr 1 cpu writes byte 2 to spdr, queueing byte 2 cpu writes byte 1 to spdr, clearing spte bit. byte 1 transfers from transmit data 3 1 2 2 3 5 register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set. (cpha:cpol = 1:0) non-disclosure agreement required serial peripheral interface module (spi) technical data MC68HC708MP16 ? rev. 3.1 264 serial peripheral interface module (spi) freescale semiconductor for an idle master or id le slave that has no dat a loaded into its transmit buffer, the spte is set again no more than two bus cycles after the transmit buffer empties in to the shift register. th is allows the user to queue up a 16-bit value to send. for an already active slave, the load of the shift register cannot occur until the transm ission is completed. this implies that a back-to-ba ck write to the transmit data register is not possible. the spte indicates when the next write can occur. 13.8 error conditions the following flags signal spi error conditions: overflow (ovrf) ? fai ling to read the spi data register before the next full byte ent ers the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read. ovrf is in the spi status and control register. mode fault error (m odf) ? the modf bit indicates that the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. modf is in the sp i status and control register. 13.8.1 overflow error the overflow flag (ovrf) be comes set if the receiv e data register still has unread data from a previous trans mission when the capture strobe of bit 1 of the next tr ansmission occurs. the bit 1 capture strobe occurs in the middle of spsck cycle 7. (see figure 13-4 and figure 13-6 .) if an overflow occurs, all data received after the overflow and before the ovrf bit is cleared does not transfer to the re ceive data register and does not set the spi rece iver full bit (sprf). the unr ead data that transferred to the receive data register before t he overflow occurred can still be read. therefore, an overflow error always indica tes the loss of data. clear the overflow flag by reading the spi status and control register and then reading the spi data register. serial peripheral interface module (spi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial peripheral interface module (spi) 265 non-disclosure agreement required ovrf generates a receiv er/error cpu interrupt request if the error interrupt enable bit ( errie) is also set. when the dmas bit is low, the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. (see figure 13-11 .) it is not possible to enable modf or ovrf individually to generate a receiver/e rror cpu interrupt request. however, leaving modfen low prevent s modf from being set. if the cpu sprf interr upt is enabled and the o vrf interrupt is not, watch for an over flow condition. figure 13-9 shows how it is possible to miss an overflow. the first part of figure 13-9 shows how it is possible to read the spscr and spdr to clear t he sprf without problems. however, as illustrated by the se cond transmission example, the ovrf bit can be set in between the ti me that spscr and spdr are read. figure 13-9. missed read of overflow condition read read ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit, byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is not cleared. byte 4 is lost. and ovrf bit clear. and ovrf bit clear. spscr spdr non-disclosure agreement required serial peripheral interface module (spi) technical data MC68HC708MP16 ? rev. 3.1 266 serial peripheral interface module (spi) freescale semiconductor in this case, an overflow can eas ily be missed. sinc e no more sprf interrupts can be generated until this ovrf is serv iced, it is not obvious that bytes are being lost as more transmissions are completed. to prevent this, either enabl e the ovrf interrupt or do another read of the spscr following the read of the spdr. this ens ures that the ovrf was not set before the sprf was clea red and that future transmissions can set the sprf bit. figure 13-10 illustrates this pr ocess. generally, to avoid this second spscr read, enable the ovrf to the cpu by setting the errie bit. figure 13-10. clearing s prf when ovrf interr upt is not enabled read read ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, cpu reads spscr again byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, cpu reads spscr again cpu reads byte 2 spdr, byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, cpu reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear. spscr spdr serial peripheral interface module (spi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial peripheral interface module (spi) 267 non-disclosure agreement required 13.8.2 mode fault error setting the spmstr bit selects master mode and configures the spsck and mosi pins as output s and the miso pin as an input. clearing spmstr selects slave mode and configur es the spsck and mosi pins as inputs and the miso pin as an output. the mode fault bit, modf, becomes set any time the st ate of the slave select pin, ss , is inconsistent with the mode select ed by spmstr. to prevent spi pin contention and damage to the mcu, a mode faul t error occurs if: the ss pin of a slave spi goes high during a transmission the ss pin of a master spi goes low at any time. for the modf flag to be set, the mode fault er ror enable bit (modfen) must be set. clearing th e modfen bit does not cl ear the modf flag but does prevent modf from being se t again after modf is cleared. modf generates a receiver/error cp u interrupt request if the error interrupt enable bit ( errie) is also set. when the dmas bit is low, the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. (see figure 13-11 .) it is not possible to enable modf or ovrf individually to generate a receiver/e rror cpu interrupt request. however, leaving modfen low prevent s modf from being set. in a master spi with th e mode fault enable bit (m odfen) set, the mode fault flag (modf) is set if ss goes to logic 0. a m ode fault in a master spi causes the following events to occur: if errie = 1, the spi generates an spi receiver/error cpu interrupt request. the spe bit is cleared. the spte bit is set. the spi state counter is cleared. the data direction regi ster of the shared i/o port regains control of port drivers. note: to prevent bus contention with another master spi after a mode fault error, clear all spi bits of the data direction regist er of the shared i/o port before enabling the spi. non-disclosure agreement required serial peripheral interface module (spi) technical data MC68HC708MP16 ? rev. 3.1 268 serial peripheral interface module (spi) freescale semiconductor when configured as a slave (spmstr = 0), the modf fl ag is set if ss goes high during a trans mission. when cpha = 0, a transmission begins when ss goes low and ends once the in coming spsck goes back to its idle level following the shift of t he eighth data bit. w hen cpha = 1, the transmission begins when the sps ck leaves its idle level and ss is already low. the transmission continues until the spsck returns to its idle level following the shif t of the last data bit. (see 13.6 transmission formats .) note: setting the modf flag does not clear the spmstr bit. the spmstr bit has no function when spe = 0. reading spmstr when modf = 1 shows the difference between a modf occurring when the spi is a master and when it is a slave. when cpha = 0, a modf occurs if a slave is selected (ss is at logic 0) and later unselected (ss is at logic 1) even if no spsck is sent to that slave. this happens because ss at logic 0 indicate s the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then later unselected with no transmission occurri ng. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = 0), t he modf bit generates an spi receiver/error cpu interr upt request if the errie bit is set. the modf bit does not clear th e spe bit or reset the spi in any way. software can abort the spi transmission by clear ing the spe bit of the slave. note: a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. to clear the modf flag, read the sp scr with the modf bit set and then write to the spcr register. this ent ire clearing mechanism must occur with no modf condition existing or else the flag is not cleared. serial peripheral interface module (spi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial peripheral interface module (spi) 269 non-disclosure agreement required 13.9 interrupts four spi status flags can be enabled to generate cpu interrupt requests: reading the spi status and control register with sprf set and then reading the receive data register clears sprf. the clearing mechanism for the spte flag is always just a write to the trans mit data register. the spi transmitter inte rrupt enable bit (sptie ) enables the spte flag to generate transmitter cpu interrupt requests, pr ovided that the spi is enabled (spe = 1). the spi receiver interrupt enable bit (sprie) enables t he sprf bit to generate receiver cpu interrupt requests , regardless of the state of the spe bit. (see figure 13-11 .) the error interrupt enable bit (e rrie) enables both the modf and ovrf bits to generate a receiv er/error cpu in terrupt request. the mode fault enable bit (m odfen) can prevent t he modf flag from being set so that only the ovrf bit is enabled by the errie bit to generate receiver/error c pu interrupt requests. table 13-2. spi interrupts flag request spte (transmitter empty) spi transmitter cpu interrupt request (dmas = 0, sptie = 1,spe = 1) sprf (receiverfull) spi receiver cpu interrupt request (dmas = 0, sprie = 1) ovrf (overflow) spi receiver/error interrupt request (errie = 1) modf (mode fault) spi receiver/error interrupt request (errie = 1) non-disclosure agreement required serial peripheral interface module (spi) technical data MC68HC708MP16 ? rev. 3.1 270 serial peripheral interface module (spi) freescale semiconductor figure 13-11. sp i interrupt r equest generation the following sources in the spi stat us and control register can generate cpu interrupt requests: spi receiver full bit (sprf) ? the sprf bit becomes set every time a byte transfers from the sh ift register to the receive data register. if the spi receiver interr upt enable bit, sprie, is also set, sprf generates an spi receiver /error cpu interrupt request. spi transmitter empty (spte) ? the spte bit becomes set every time a byte transfers from the tr ansmit data regist er to the shift register. if the spi trans mit interrupt enable bit, sptie, is also set, spte generates an spte cpu interrupt request. not available spte sptie sprf sprie dmas errie modf ovrf spe spi transmitter cpu interrupt request not available spi receiver/error cpu interrupt request serial peripheral interface module (spi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial peripheral interface module (spi) 271 non-disclosure agreement required 13.10 resetting the spi any system reset completely resets the spi. partial resets occur whenever the spi enable bit (spe) is low. whenever spe is low, the following occurs: the spte flag is set any transmission currently in progress is aborted the shift register is cleared the spi state counter is cleared, making it ready for a new complete transmission all the spi port logi c is defaulted back to being general purpose i/o. the following items are rese t only by a system reset: all control bits in the spcr register all control bits in the spscr register (modfen, errie, spr1, and spr0) the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe between transmissions wit hout having to set all c ontrol bits again when spe is set back high fo r the next transmission. by not resetting the spr f, ovrf, and modf flags , the user can still service these interrupts after the spi has been disabl ed. the user can disable the spi by writing 0 to the spe bit. the spi can also be disabled by a mode fault occuring in an spi th at was configured as a master with the modfen bit set. non-disclosure agreement required serial peripheral interface module (spi) technical data MC68HC708MP16 ? rev. 3.1 272 serial peripheral interface module (spi) freescale semiconductor 13.11 low-power mode the wait instruction puts the mcu in a low-power-consumption stand- by mode. the spi module remains active after the execution of a wait instruction. in wait mode the spi module registers are no t accessible by the cpu. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabl ing the spi module befor e executing the wait instruction. 13.12 spi during break interrupts the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during t he break state. (see section 7. system integration module (sim) .) to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect status bits du ring the break state, writ e a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), software can read and write i/o registers during the break state wi thout affecting status bits. some status bits have a two-step read/wr ite clearing proce dure. if software does the first step on su ch a bit before the br eak, the bit cannot change during the break state as long as bcf e is at logic 0. after the break, doing the second step cl ears the status bit. since the spte bit cannot be cleared during a break with the bcfe bit cleared, a write to the transmit data register in break mode does not initiate a transmission, nor is this data transferred into the shift register. therefore, a write to t he spdr in break mode with the bcfe bit cleared has no effect. serial peripheral interface module (spi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial peripheral interface module (spi) 273 non-disclosure agreement required 13.13 i/o signals the spi module has five i/o pins and shares four of them with a parallel i/o port. miso ? data received mosi ? data transmitted spsck ? serial clock ss ? slave select cgnd ? clock ground the spi has limited inte r-integrated circuit (i 2 c) capability (requiring software support) as a master in a single-master environment. to communicate with i 2 c peripherals, mosi becom es an open-drain output when the spwom bit in the spi control regi ster is set. in i 2 c communication, the mo si and miso pins are connected to a bidirectional pin from the i 2 c peripheral and through a pullup resistor to v dd . 13.13.1 miso (master in/slave out) miso is one of the two spi module pins that transmits serial data. in full duplex operation, the miso pin of the mast er spi module is connected to the miso pin of the slave spi m odule. the master spi simultaneously receives data on its mi so pin and transmits dat a from its mosi pin. slave output data on the miso pin is enabl ed only when the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is logic 0 and its ss pin is at logic 0. to support a multiple- slave system, a logic 1 on the ss pin puts the miso pin in a high- impedance state. when enabled, the spi controls dat a direction of the miso pin regardless of the state of the data direction regi ster of the shared i/o port. non-disclosure agreement required serial peripheral interface module (spi) technical data MC68HC708MP16 ? rev. 3.1 274 serial peripheral interface module (spi) freescale semiconductor 13.13.2 mosi (master out/slave in) mosi is one of the two spi module pins that transmits serial data. in full duplex operation, the mosi pin of the mast er spi module is connected to the mosi pin of the slave spi m odule. the master spi simultaneously transmits data from it s mosi pin and receives data on its miso pin. when enabled, the spi controls dat a direction of the mosi pin regardless of the state of the data direction regi ster of the shared i/o port. 13.13.3 spsck (serial clock) the serial clock synchronizes dat a transmission between master and slave devices. in a master mcu, the spsck pin is the cl ock output. in a slave mcu, the spsck pin is the clo ck input. in full duplex operation, the master and slave mcus exchange a by te of data in eight serial clock cycles. when enabled, the spi controls dat a direction of the spsck pin regardless of the state of the data direction regi ster of the shared i/o port. 13.13.4 ss (slave select) the ss pin has various func tions depending on the cu rrent state of the spi. for an spi configur ed as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the start of a transmission. (see 13.6 transmission formats .) since it is used to i ndicate the start of a transmission, the ss must be toggled high and low between each byte transmitted for the cpha = 0 format . however, it can remain low between transmissions for the cpha = 1 format. see figure 13-12 . serial peripheral interface module (spi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial peripheral interface module (spi) 275 non-disclosure agreement required figure 13-12. cpha/ss timing when an spi is configur ed as a slave, the ss pin is always configured as an input. it cannot be used as a general purpose i/o regardless of the state of the modfen control bit. however, the modfen bit can still prevent the state of the ss from creating a modf error. (see 13.14.2 spi status and control register .) note: a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high- impedance state. the slave spi ignor es all incoming spsck clocks, even if it was already in t he middle of a transmission. when an spi is configur ed as a master, the ss input can be used in conjunction with the modf flag to prevent multip le masters from driving mosi and spsck. (see 13.8.2 mode fault error .) for the state of the ss pin to set the modf flag, the modfen bit in the spsck register must be set. if the modfen bit is low for an spi master, the ss pin can be used as a general purpose i/o under the control of the data direction register of the shared i/o port. with modfen high, it is an input-only pin to the spi regardle ss of the state of the data direction regi ster of the shared i/o port. the cpu can always read the state of the ss pin by configuring the appropriate pin as an input and readi ng the port data register. (see table 13-3 .) byte 1 byte 3 miso/mosi byte 2 master ss slave ss (cpha = 0) slave ss (cpha = 1) non-disclosure agreement required serial peripheral interface module (spi) technical data MC68HC708MP16 ? rev. 3.1 276 serial peripheral interface module (spi) freescale semiconductor 13.13.5 cgnd (clock ground) cgnd is the ground retu rn for the serial cl ock pin, spsck, and the ground for the port output bu ffers. to reduce the gr ound return path loop and minimize radio frequen cy (rf) emissions, connect the ground pin of the slave to the cgnd pin of the master. 13.14 i/o registers three registers control and monitor spi operation: spi control register (spcr) spi status and cont rol register (spscr) spi data register (spdr) table 13-3. spi configuration spe spmstr modfen spi configuration state of ss logic 0x (1) 1. x = don?t care x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input-only to spi 1 1 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input-only to spi serial peripheral interface module (spi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial peripheral interface module (spi) 277 non-disclosure agreement required 13.14.1 spi control register the spi control register does the following: enables spi modul e interrupt requests selects cpu interrupt requests configures the spi modul e as master or slave selects serial clock polarity and phase configures the spsck, mosi, and miso pins as open-drain outputs enables the spi module sprie ? spi receiver interrupt enable bit this read/write bi t enables cpu interrupt re quests generated by the sprf bit. the sprf bit is set when a byte transfers from the shift register to the receive data r egister. reset clear s the sprie bit. 1 = sprf cpu interrupt requests 0 = sprf cpu interrupt requests dmas ?dma select bit this read-only bit has no effect on this versi on of the spi. this bit always reads as a 0. 0 = sprf dma and spte dm a service requests disabled (sprf cpu and spte cpu interrup t requests enabled) spmstr ? spi master bit address: $001b bit 7654321bit 0 read: sprie dmas spmstr cpol cpha spwom spe sptie write: reset:00101000 = unimplemented figure 13-13. spi cont rol register (spcr) non-disclosure agreement required serial peripheral interface module (spi) technical data MC68HC708MP16 ? rev. 3.1 278 serial peripheral interface module (spi) freescale semiconductor this read/write bit sele cts master mode oper ation or slave mode operation. reset sets the spmstr bit. 1 = master mode 0 = slave mode cpol ? clock polarity bit this read/write bit det ermines the logic st ate of the spsck pin between transmissions. ( figure 13-4 and figure 13-6 .) to transmit data between spi modules , the spi modules must have identical cpol values. reset clears the cpol bit. cpha ? clock phase bit this read/write bit contro ls the timing relationship between the serial clock and spi data. (see figure 13-4 and figure 13-6 .) to transmit data between spi modules , the spi modules must have identical cpha values. when cpha = 0, the ss pin of the sl ave spi module must be set to logic 1 between bytes. (see figure 13-12 .) reset sets the cpha bit. spwom ? spi wired-or mode bit this read/write bit disables th e pull-up devices on pins spsck, mosi, and miso so t hat those pins becom e open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull sp sck, mosi, and miso pins spe ? spi enable this read/write bi t enables the spi module. clearing spe causes a partial reset of the spi. (see 13.10 resetting the spi .) reset clears the spe bit. 1 = spi module enabled 0 = spi module disabled sptie? spi transmit interrupt enable this read/write bi t enables cpu interrupt re quests generated by the spte bit. spte is set when a byte transfers fr om the transmit data register to the shif t register. reset cl ears the sptie bit. 1 = spte cpu interr upt requests enabled 0 = spte cpu interr upt requests disabled serial peripheral interface module (spi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial peripheral interface module (spi) 279 non-disclosure agreement required 13.14.2 spi status and control register the spi status and control register cont ains flags to signal the following conditions: receive data register full failure to clear sprf bit before next byte is received (overflow error) inconsistent logic level on ss pin (mode fault error) transmit data r egister empty the spi status and control register also contains bits that perform the following functions: enable error interrupts enable mode fault error detection select master spi baud rate sprf ? spi receiver full bit this clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. sprf generates a cpu interrupt request if the s prie bit in the spi contro l register is set also. during an sprf cpu interrupt, the cpu clea rs sprf by reading the spi status and control register wi th sprf set and then reading the spi data register. reset clears the sprf bit. 1 = receive data register full 0 = receive data register not full address: $001c bit 7654321bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 = unimplemented figure 13-14. spi status an d control register (spscr) non-disclosure agreement required serial peripheral interface module (spi) technical data MC68HC708MP16 ? rev. 3.1 280 serial peripheral interface module (spi) freescale semiconductor errie ? error interrupt enable bit this read/write bit enabl es the modf and ovrf bits to generate cpu interrupt requests. re set clears t he errie bit. 1 = modf and ovrf can generat e cpu interrupt requests 0 = modf and ovrf cannot gener ate cpu interrupt requests ovrf ? overflow bit this clearable, read- only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. in an overflow condition, th e byte already in the receive data register is unaffected, and t he byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and then reading the receive data regi ster. reset clears the ovrf bit. 1 = overflow 0 = no overflow modf ? mode fault bit this clearable, read-only flag is set in a slave spi if the ss pin goes high during a transmission with the modfen bit set. in a master spi, the modf flag is set if the ss pin goes low at any time with the modfen bit set. clear the modf bi t by reading the spi status and control register (sp scr) with modf set and t hen writing to the spi control register (spcr). reset clears the modf bit. 1 = ss pin at inappropriate logic level 0 = ss pin at appropria te logic level spte ? spi transmi tter empty bit this clearable, read-only flag is set each time t he transmit data register transfers a by te into the shift regi ster. spte generates an spte cpu interrupt request if the sptie bit in t he spi contro l register is set also. note: do not write to the spi data r egister unless the spte bit is high. during an spte cpu interrupt, the cpu cl ears the spte bit by writing to the transmit data register. reset sets the spte bit. 1 = transmit data register empty 0 = transmit data r egister not empty serial peripheral interface module (spi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial peripheral interface module (spi) 281 non-disclosure agreement required modfen ? mode fault enable bit this read/write bit, when set to 1, allows the modf flag to be set. if the modf flag is set, clearing the modfen does not clear the modf flag. if the spi is enabled as a master and the modfen bit is low, then the ss pin is available as a general purpose i/o. if the modfen bit is set, then this pin is not avail able as a general purpose i/o. when t he spi is enabled as a slave, the ss pin is not available as a general purpose i/ o regardless of the value of modfen. (see 13.13.4 ss (sl ave select) .) if the modfen bit is lo w, the level of the ss pin does not affect the operation of an enabled spi config ured as a master. for an enabled spi configured as a slave, havin g modfen low only prevents the modf flag from being se t. it does not affect any other part of spi operation. (see 13.8.2 mode fault error .) spr1 and spr0 ? spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 13-4 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. use the following formula to calculate the spi baud rate: where: cgmout = base clock output of the clock generator module (cgm) bd = baud rate divisor table 13-4. spi master baud rate selection spr1:spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 baud rate cgmout 2bd -------------- ------------ = non-disclosure agreement required serial peripheral interface module (spi) technical data MC68HC708MP16 ? rev. 3.1 282 serial peripheral interface module (spi) freescale semiconductor 13.14.3 spi data register the spi data register consists of t he read-only receive data register and the write-only transmit data register . writing to the spi data register writes data into the transmit data r egister. reading the spi data register reads data from the rece ive data register. the tr ansmit data and receive data registers are separat e registers that can c ontain different values. (see figure 13-1 .) r7:r0/t7:t0 ? receive/ transmit data bits note: do not use read-modi fy-write instructions on t he spi data register since the register read is not the same as th e register written. address: $001d bit 7654321bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset figure 13-15. spi data register (spdr) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 283 non-disclosure agreement required technical data ? MC68HC708MP16 section 14. serial communications interface module (sci) 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 14.4.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14.4.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14.4.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14.4.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 289 14.4.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 14.4.2.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 14.4.2.5 inversion of transm itted output. . . . . . . . . . . . . . . . . . . 292 14.4.2.6 transmitter in terrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .292 14.4.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 14.4.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 14.4.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 14.4.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 14.4.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 14.4.3.5 receiver wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 14.4.3.6 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 14.4.3.7 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 14.5 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 14.6 sci during break module interrupts. . . . . . . . . . . . . . . . . . . .299 14.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 14.7.1 ptf5/txd (transmit data ) . . . . . . . . . . . . . . . . . . . . . . . . 300 14.7.2 ptf4/rxd (receive data ). . . . . . . . . . . . . . . . . . . . . . . . . 300 non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 284 serial communications interface module (sci) freescale semiconductor 14.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 14.8.1 sci control regi ster 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .301 14.8.2 sci control regi ster 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .304 14.8.3 sci control regi ster 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .307 14.8.4 sci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 14.8.5 sci status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 14.8.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314 14.8.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . 314 14.2 introduction this section describes the serial co mmunications interf ace module (sci, version d), which allows high- speed asynchronous communications with peripheral devic es and other mcus. 14.3 features features of the sci module include: full duplex operation standard mark/space non-re turn-to-zero (nrz) format 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled trans mitter and receiver separate receiver and transmi tter cpu interrupt requests separate receiver and transmitter programmable transm itter output polarity two receiver wake-up methods: ? idle line wake-up ? address mark wake-up serial communications interface module (sci) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 285 non-disclosure agreement required interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framin g error detection hardware parity checking 1/16 bit-time noise detection 14.4 functional description figure 14-1 shows the structure of the sc i module. the sci allows full- duplex, asynchronous, nrz serial communication among the mcu and remote devices, including other mcus . the transmitter and receiver of the sci operate independent ly, although they us e the same baud rate generator. during normal oper ation, the cpu monitors the status of the sci, writes the data to be transmi tted, and processes received data. non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 286 serial communications interface module (sci) freescale semiconductor figure 14-1. sci m odule block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wake-up pty pen register transmitter interrupt control receiver interrupt control error interrupt control control ensci loops ensci ptf4/rxd ptf5/txd internal bus txinv loops 4 16 pre- scaler baud rate generator f bus serial communications interface module (sci) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 287 non-disclosure agreement required addr. name bit 7 6 5 4 3 2 1 bit 0 $0038 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty wfite: reset: 0 0 0 0 0 0 0 0 $0039 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $003a sci control register 3 (scc3) read: r8 t8 00 orie neie feie peie write: reset: u u 0 0 0 0 0 0 $003b sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset: 1 1 0 0 0 0 0 0 $003c sci status register 2 (scs2) read: bkf rpf write: reset: 0 0 0 0 0 0 0 0 $003d sci data register (scdr) read: bit 7 6 5 4 3 2 1 bit 0 write: reset: unaffected by reset $003e sci baud rate register (scbr) read: scp1 scp0 r scr2 scr1 scr0 write: reset: 0 0 0 0 0 0 0 0 = unimplemented r = reserved u = unaffected figure 14-2. sci i/o register summary non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 288 serial communications interface module (sci) freescale semiconductor 14.4.1 data format the sci uses the standard non-return-to-zero mark /space data format illustrated in figure 14-3 . figure 14-3. sci data formats 14.4.2 transmitter figure 14-4 shows the structure of the sci transmitter. 14.4.2.1 character length the transmitter can accommod ate either 8-bit or 9- bit data. the state of the m bit in sci control register 1 (scc1) deter mines character length. when transmitting 9-bit data, bit t8 in sci control register 3 (scc3) is the ninth bi t (bit 8). bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format (bit m in scc1 clear) start bit bit 0 next stop bit start bit 9-bit data format (bit m in scc1 set) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 possible parity bit possible parity bit serial communications interface module (sci) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 289 non-disclosure agreement required 14.4.2.2 character transmission during an sci transmission, the transmit shift regist er shifts a character out to the ptf5/txd pin. the sci data register ( scdr) is the write-only buffer between the internal data bus and the transmi t shift register. to initiate an sci transmission: 1. enable the sci by writing a logi c 1 to the enable sci bit (ensci) in sci control r egister 1 (scc1). 2. enable the transmitter by writi ng a logic 1 to the transmitter enable bit (te) in sci cont rol register 2 (scc2). 3. clear the sci transmit ter empty bit by first reading sci status register 1 (scs1) and t hen writing to the scdr. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, tran smitter control logic automatically loads the transmit shift register with a preamble of logic 1s. after the preamble shifts out, control logic tr ansfers the scdr data into the transmit shift register. a logic 0 start bit automati cally goes into the least significant bit position of the transmit shift register. a lo gic 1 stop bit goes into the most signi ficant bit position. the sci transmitter empt y bit, scte, in scs1 becomes set when the scdr transfers a byte to the trans mit shift register. the scte bit indicates that the scdr c an accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmi tter cpu interrupt request. when the transmit shift register is not transmitting a character, the ptf5/txd pin goes to the id le condition, logic 1. if at any time software clears the ensci bit in sci control register 1 (s cc1), the transmitter and receiver relinquish contro l of the port f pins. non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 290 serial communications interface module (sci) freescale semiconductor figure 14-4. sci transmitter pen pty h876543210l 11-bit transmit stop start t8 scte sctie tcie sbk tc f bus parity generation msb sci data register load from scdr shift enable preamble (all ones) break (all zeros) transmitter control logic shift register tc sctie tcie scte transmitter cpu interrupt request m ensci loops te ptf5/txd txinv internal bus 4 pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider 16 serial communications interface module (sci) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 291 non-disclosure agreement required 14.4.2.3 break characters writing a logic 1 to the send break bit, sbk, in scc2 loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit in scc1. as long as sbk is at logi c 1, transmitter logic continuously loads break characters in to the transmit shif t register. after software clears the sbk bit, the shif t register finishes transmitting the last break character and then tr ansmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the nex t character. the sci recognizes a break character when a start bit is followed by 8 or 9 logic 0 data bits an d a logic 0 where the stop bit should be. receiving a break character has the foll owing effects on sci registers: sets the framing erro r bit (fe) in scs1 sets the sci receiver full bit (scrf) in scs1 clears the sci dat a register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception in prog ress flag (rpf) bits 14.4.2.4 idle characters an idle character contains all logic 1s and has no st art, stop, or parity bit. idle character length depends on the m bit in scc1. th e preamble is a synchronizing idle character that begins every transmission. if the te bit is clear ed during a transmission, t he ptf5/txd pin becomes idle after completion of the transmission in pr ogress. clearing and then setting the te bit duri ng a transmission queues an id le character to be sent after the character currently being transmitted. note: when queueing an idle character, return the te bit to logic 1 before the stop bit of the current character shifts out to the ptf5/txd pi n. setting non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 292 serial communications interface module (sci) freescale semiconductor te after the stop bit appears on ptf5/txd causes data previously written to the scdr to be lost. a good time to toggle the te bit is when the scte bit becomes set and just before writing the next byte to the scdr. 14.4.2.5 inversion of transmitted output the transmit inversion bit (txinv) in sci control r egister 1 (scc1) reverses the polarity of transmitted da ta. all transmitted values, including idle, break, start, and stop bits, are inverted when txinv is at logic 1. (see 14.8.1 sci control register 1 .) 14.4.2.6 transmitter interrupts the following conditions c an generate cpu interr upt requests from the sci transmitter: sci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can gene rate a transmitter cp u interrupt request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generat e transmitter cpu interrupt requests. transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are em pty and that no break or idle character has been generated. th e transmission complete interrupt enable bit, tcie , in scc2 enables the tc bit to generate transmitter cpu interrupt requests. serial communications interface module (sci) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 293 non-disclosure agreement required 14.4.3 receiver figure 14-5 shows the structure of the sci receiver. figure 14-5. sci receiver block diagram all ones all zeros m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery or orie nf neie fe feie pe peie scrie scrf ilie idle wake-up logic parity checking msb error cpu interrupt request cpu interrupt request sci data register r8 orie neie feie peie scrie ilie rwu scrf idle or nf fe pe ptf4/rx internal bus pre- scaler baud divider 4 16 scp1 scp0 scr2 scr1 scr0 f bus non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 294 serial communications interface module (sci) freescale semiconductor 14.4.3.1 character length the receiver can accommodat e either 8-bit or 9-bi t data. the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bit data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when rece iving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 14.4.3.2 character reception during an sci re ception, the receive shift regi ster shifts characters in from the ptf4/rxd pin. the sci data register (sc dr) is the read-only buffer between the inter nal data bus and the re ceive shift register. after a complete character shifts into the receive shift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status regi ster 1 (scs1) becomes se t, indicating that the received byte can be read. if the sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bi t generates a receiver cpu interrupt request. 14.4.3.3 data sampling the receiver samples the ptf4/rxd pin at the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at the following times (see figure 14-6 ): after every start bit after the receiver detects a data bit change from l ogic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 return a valid logic 1 and the majo rity of the next rt8, rt9, and rt10 samples return a valid logic 0) to locate the start bit, data recovery logic does an asyn chronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. serial communications interface module (sci) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 295 non-disclosure agreement required figure 14-6. receiver data sampling to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 14-1 summarizes t he results of the start bit verification samples. if start bit verification is not successf ul, the rt clock is reset and a new search for a start bit begins. rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb ptf4/rxd table 14-1. start bit verification rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 296 serial communications interface module (sci) freescale semiconductor to determine the value of a data bit and to detect noise, recovery logic takes samples at r t8, rt9, and rt10. table 14-2 summarizes the results of the data bit samples. note: the rt8, rt9, and rt10 samp les do not affect star t bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verifica tion, the noise flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 14-3 summarizes the resu lts of the stop bit samples. table 14-2. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 14-3. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 serial communications interface module (sci) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 297 non-disclosure agreement required 14.4.3.4 framing errors if the data recovery l ogic does not detect a logi c 1 where the stop bit should be in an in coming character, it sets t he framing error bit, fe, in scs1. the fe flag is set at the same time that the scrf bit is set. a break character that has no stop bit also sets the fe bit. 14.4.3.5 receiver wake-up so that the mcu can ignore tr ansmissions intended only for other receivers in multiple-receiver system s, the receiver can be put into a standby state. setting the receiver wa ke-up bit, rwu, in scc2 puts the receiver into a standby state during which re ceiver interrupts are disabled. depending on the state of the wake bit in scc1, either of two conditions on the ptf4/rxd pin can bring the receiv er out of the standby state: address mark ? an address mark is a logic 1 in the most significant bit position of a rece ived character. when the wake bit is set, an address mark wakes t he receiver from the standby state by clearing the rwu bit. the addr ess mark also sets the sci receiver full bit, scrf. software can then compare the character containing the address mark to the user-defined address of the receiver. if they ar e the same, the receiv er remains awake and processes the characters that fo llow. if they are not the same, software can set the rwu bit and put the rece iver back into the standby state. idle input line condition ? when the wake bit is clear, an idle character on the ptf4/rxd pin wakes the receiver from the standby state by clearing the rw u bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the sci receiver full bit, scrf. the id le line type bit, ilty, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. note: clearing the wake bit af ter the ptf4/rxd pin has been idle can cause the receiver to wa ke up immediately. non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 298 serial communications interface module (sci) freescale semiconductor 14.4.3.6 receiver interrupts the following sources can gene rate cpu interrupt re quests from the sci receiver: sci receiver full ( scrf) ? the scrf bit in scs1 indicates that the receive shift register has tran sferred a characte r to the scdr. scrf can generate a receiver cp u interrupt request. setting the sci receive interrupt enable bit, s crie, in scc2 enables the scrf bit to generate rece iver cpu interrupts. idle input (idle) ? the idle bit in scs1 i ndicates that 10 or 11 consecutive logic 1s shifted in from the ptf4/rxd pin. the idle line interrupt enable bi t, ilie, in scc2 enables the idle bit to generate cpu inte rrupt requests. 14.4.3.7 error interrupts the following receiver error flags in scs1 can generat e cpu interrupt requests: receiver overrun (or) ? the or bit indicates that the receive shift register shifted in a new character before the previous character was read from the scdr. the previous character remains in the scdr, and the new character is lost. the overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. noise flag (nf) ? the nf bit is set when the sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enabl e bit, neie, in scc3 enables nf to generate sci erro r cpu interrupt requests. framing error (fe) ? the fe bit in scs1 is se t when a logic 0 occurs where the receiver expec ts a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. parity error (pe) ? the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in scc3 enables pe to gener ate sci error cpu interrupt requests. serial communications interface module (sci) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 299 non-disclosure agreement required 14.5 wait mode the wait and stop in structions put the mcu in low-power- consumption standby modes. the sci module remains active af ter the execution of a wait instruction. in wait m ode the sci module register s are not accessible by the cpu. any enabled c pu interrupt request fr om the sci module can bring the mcu out of wait mode. if sci module functions are not requ ired during wait mode, reduce power consumption by disabling the m odule before executing the wait instruction. 14.6 sci during break module interrupts the system integration module (sim) contro ls whether status bits in other modules can be cleared during inte rrupts generated by the break module. the bcfe bit in the sim break flag control register (sbfcr) enables software to cl ear status bits durin g the break state. to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect status bits du ring the break state, writ e a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), software can read and write i/o registers during the break state wi thout affecting status bits. some status bits have a two-step read/wr ite clearing proce dure. if software does the first step on su ch a bit before the br eak, the bit cannot change during the break state as long as bcf e is at logic 0. after the break, doing the second step cl ears the status bit. non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 300 serial communications interface module (sci) freescale semiconductor 14.7 i/o signals port f shares two of it s pins with the sci modu le. the two sci i/o pins are: ptf5/txd ? transmit data ptf4/rxd ? receive data 14.7.1 ptf5/txd (transmit data) the ptf5/txd pin is the serial data output from th e sci transmitter. the sci shares the ptf5/tx d pin with port f. when the sci is enabled, the ptf5/txd pin is an out put regardless of the st ate of the ddrf5 bit in data direction register f (ddrf). 14.7.2 ptf4/rxd (receive data) the ptf4/rxd pin is the serial data input to th e sci receiver. the sci shares the ptf4/rxd pin with port f. when the sci is enabled, the ptf4/rxd pin is an input regardless of the stat e of the ddrf4 bit in data direction register f (ddrf). 14.8 i/o registers the following i/o registers con trol and monitor sci operation: sci control register 1 (scc1) sci control register 2 (scc2) sci control register 3 (scc3) sci status register 1 (scs1) sci status register 2 (scs2) sci data register (scdr) sci baud rate register (scbr) serial communications interface module (sci) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 301 non-disclosure agreement required 14.8.1 sci control register 1 sci control register 1: enables loop mode operation enables the sci controls output polarity controls character length controls sci wake-up method controls idle character detection enables parity function controls parity type loops ? loop mode select bit this read/write bit enabl es loop mode operatio n. in loop mode the pte6/rxd pin is disconnected from the sci, and the transmitter output goes into the rece iver input. both t he transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable sci bit this read/write bit enabl es the sci and the sc i baud rate generator. clearing ensci sets the scte and tc bits in sc i status register 1 and disables transmitter interrupt s. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled address: $0038 bit 7654321bit 0 read: loops ensci txinv m wake ilty pen pty write: reset:00000000 figure 14-7. sci cont rol register 1 (scc1) non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 302 serial communications interface module (sci) freescale semiconductor txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter out put not inverted note: setting the txinv bit inve rts all transmitted values , including idle, break, start, and stop bits. m ? mode (character length) bit this read/write bit deter mines whether sci characters are eight or nine bits long. (see table 14-4 .) the ninth bit can serve as an extra stop bit, as a receiver wake-up si gnal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ? wake-up condition bit this read/write bit deter mines which condition wakes up the sci: a logic 1 (address mark) in the most si gnificant bit posi tion of a received character or an idle condition on t he pte6/rxd pin. reset clears the wake bit. 1 = address mark wake-up 0 = idle line wake-up ilty ? idle line type bit this read/write bit deter mines when the sci star ts counting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but re quires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit c ount begins afte r stop bit 0 = idle character bit c ount begins after start bit serial communications interface module (sci) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 303 non-disclosure agreement required pen ? parity enable bit this read/write bit ena bles the sci pari ty function. (see table 14-4 .) when enabled, the parity function in serts a parity bit in the most significant bit position. (see figure 14-3 .) reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled pty ? parity bit this read/write bit determines w hether the sci generates and checks for odd parity or even parity. (see table 14-4 .) reset clears the pty bit. 1 = odd parity 0 = even parity note: changing the pty bit in the middle of a transmission or reception can generate a parity error. table 14-4. character format selection control bits character format mpen:pty start bits data bits parity stop bits character length 0 0x 1 8 none 1 10 bits 1 0x 1 9 none 1 11 bits 010 17even1 10 bits 0 11 1 7 odd 1 10 bits 110 18even1 11 bits 1 11 1 8 odd 1 11 bits non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 304 serial communications interface module (sci) freescale semiconductor 14.8.2 sci control register 2 sci control register 2: enables the following cpu interrupt requests: ? enables the scte bit to gener ate transmitter cpu interrupt requests ? enables the tc bi t to generate transmi tter cpu interrupt requests ? enables the scrf bit to gener ate receiver cpu interrupt requests ? enables the idle bit to gene rate receiver cpu interrupt requests enables the transmitter enables the receiver enables sci wake-up transmits sci break characters sctie ? sci transmit interrupt enable bit this read/write bi t enables the scte bit to generate sci transmitter cpu interrupt requests. se tting the sctie bit in scc3 enables scte cpu interrupt requests. re set clears t he sctie bit. 1 = scte enabled to gener ate cpu interrupt 0 = scte not enabled to generate cpu interrupt address: $0039 bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 14-8. sci contro l register 2 (scc2) serial communications interface module (sci) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 305 non-disclosure agreement required tcie ? transmission comple te interrupt enable bit this read/write bit enable s the tc bit to generat e sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ? sci receive interrupt enable bit this read/write bi t enables the scrf bit to generate sci receiver cpu interrupt requests. setting the scrie bit in scc3 enables the scrf bit to generate c pu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to gener ate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to gener ate sci receiver cpu interrupt requests. rese t clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabl ed to generate cp u interrupt requests te ? transmitt er enable bit setting this read/write bit begin s the transmission by sending a preamble of ten or eleven logic 1s from the tran smit shift register to the ptf5/txd pin. if software clea rs the te bit, the transmitter completes any transmission in progr ess before the ptf5/txd returns to the idle cond ition (logic 1). clearing and then setting te during a transmission queues an idle characte r to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitt er enabled 0 = transmitt er disabled note: writing to the te bit is not allowed when the enab le sci bit (ensci) is clear. ensci is in sci control register 1. non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 306 serial communications interface module (sci) freescale semiconductor re ? receiver enable bit setting this read/write bit enables the receiver. clearing the re bit disables the receiver but does not a ffect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note: writing to the re bit is not allowed w hen the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu ? receiver wake-up bit this read/write bit puts the receiver in a st andby state during which receiver interrupt s are disabled. the wake bit in scc1 determines whether an idle input or an address mark brings the receiver out of the standby state and clear s the rwu bit. rese t clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting and then clearing this r ead/write bit transmits a break character followed by a logic 1. the logic 1 after the break character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously transmits break characters with no logic 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break charac ters being transmitted note: do not toggle the sbk bi t immediately after se tting the scte bit. toggling sbk too early causes the sci to send a break character instead of a preamble. serial communications interface module (sci) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 307 non-disclosure agreement required 14.8.3 sci control register 3 sci control register 3: stores the ninth sci data bit rece ived and the ninth sci data bit to be transmitted enables sci receiver full (scrf) enables sci transmi tter empty (scte) enables the foll owing interrupts: ? receiver overrun interrupts ? noise error interrupts ? framing error interrupts ? parity error interrupts r8 ? received bit 8 when the sci is receiving 9-bit char acters, r8 is the read-only ninth bit (bit 8) of the received characte r. r8 is received at the same time that the scdr receiv es the other 8 bits. when the sci is receiving 8-bit charac ters, r8 is a copy of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the sci is transmi tting 9-bit characters , t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift register at the same time that the scdr is loaded into the transmit shift register. re set has no effect on the t8 bit. address: $003a bit 76 5 4 3 2 1bit 0 read: r8 t8 00 orie neie feie peie write: reset:uu 0 0 0000 = unimplemented u = unaffected figure 14-9. sci contro l register 3 (scc3) non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 308 serial communications interface module (sci) freescale semiconductor orie ? receiver overr un interrupt enable bit this read/write bit enabl es sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt r equests from or bit enabled 0 = sci error cpu interrupt r equests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enabl es sci error cpu interrupt requests generated by the noise error bi t, ne. reset clears neie. 1 = sci error cpu interrupt r equests from ne bit enabled 0 = sci error cpu interrupt r equests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enabl es sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt r equests from fe bit disabled peie ? receiver parity error interrupt enable bit this read/write bit enabl es sci receiver cpu interrupt requests generated by the parity error bit, pe. (see 14.8.4 sci status register 1 .) reset clears peie. 1 = sci error cpu interrupt r equests from pe bit enabled 0 = sci error cpu interrupt r equests from pe bit disabled serial communications interface module (sci) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 309 non-disclosure agreement required 14.8.4 sci status register 1 sci status register 1 contains flags to signal these conditions: transfer of scdr data to trans mit shift register complete transmission complete transfer of receive shift r egister data to scdr complete receiver input idle receiver overrun noisy data framing error parity error scte ? sci transmi tter empty bit this clearable, read-only bit is set when the scdr transfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt r equest. in normal operation, clear the sct e bit by reading sc s1 with scte set and then writing to scdr. re set sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register address: $003b bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented figure 14-10. sci status register 1 (scs1) non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 310 serial communications interface module (sci) freescale semiconductor tc ? transmission complete bit this read-only bit is set when the sc te bit is set, and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is automatically cleared when data, preambl e or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency between queuei ng data, preambl e, and break and the transmission actually star ting. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ? sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf c an generate an sci receiver cpu interrupt request. w hen the scrie bit in scc2 is set, scrf generates a cpu inte rrupt request. in norm al operation, clear the scrf bit by readi ng scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is se t when ten or eleven consecutive logic 1s appear on the receiver i nput. idle generates an sci error cpu interrupt request if the ilie bit in scc2 is also set. clear the idle bit by reading scs1 with id le set and then reading the scdr. after the receiver is enabled, it must receive a valid character that sets the scrf bit before an idle condition can set the idle bit. also, after the idle bit has been cl eared, a valid characte r must again set the scrf bit before an idle condition can set the id le bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active (or id le since the idle bit was cleared) serial communications interface module (sci) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 311 non-disclosure agreement required or ? receiver overrun bit this clearable, read-only bit is se t when software fails to read the scdr before the receive shift regist er receives the next character. the or bit generates an sci error cpu interrupt request if the orie bit in scc3 is also set. the data in the shift regist er is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. rese t clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an over run to occur between reads of scs1 and scdr in the fl ag-clearing sequence. figure 14-11 shows the normal flag- clearing sequence and an example of an overrun caused by a delayed flag-clearin g sequence. the delayed read of scdr does not clear t he or bit because or was not set when scs1 was read. byte 2 caused the ov errun and is lost. the next flag- clearing sequence read s byte 3 in the scd r instead of byte 2. in applications that are subject to software la tency or in which it is important to know which byte is lost due to an ov errun, the flag- clearing routine c an check the or bit in a se cond read of scs1 after reading the data register. nf ? receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the ptf4/rxd pin. nf gener ates an nf cpu interr upt request if the neie bit in scc3 is also se t. clear the nf bit by reading scs1 and then reading the scdr. rese t clears the nf bit. 1 = noise detected 0 = no noise detected fe ? receiver framing error bit this clearable, read-only bit is set when a logic 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 312 serial communications interface module (sci) freescale semiconductor pe ? receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is al so set. clear the pe bit by reading scs1 with pe set and then readi ng the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected figure 14-11. flag clearing sequence byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr (byte 1) scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr (byte 2) scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr (byte 3) scrf = 0 byte 1 read scs1 scrf = 1 read scdr (byte 1) scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr (byte 3) delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0 serial communications interface module (sci) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 313 non-disclosure agreement required 14.8.5 sci status register 2 sci status register 2 contains flags to signal these conditions: break character detected incoming data bkf ? break flag bit this clearable, read-only bit is set when the sci detects a break character on the ptf4/rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit ch aracter transmissions, t he r8 bit in scc3 is cleared. bkf does not generate a c pu interrupt request. clear bkf by reading scs2 with bkf set and then reading th e scdr. once cleared, bkf can become set again only after logic 1s again appear on the ptf4/rxd pin followed by a nother break character. reset clears the bkf bit. 1 = break character detected 0 = no break ch aracter detected rpf ?reception in progress flag bit this read-only bit is set when the receiver detec ts a logic 0 during the rt1 time period of t he start bit search. rp f does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch, or when the receiver detects an idle character. pol ling rpf before disabling the sci module or entering stop mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress address: $003c bit 7654321bit 0 read: bkf rpf write: reset:00000000 = unimplemented figure 14-12. sci status register 2 (scs2) non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 314 serial communications interface module (sci) freescale semiconductor 14.8.6 sci data register the sci data register is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the sci data register. r7/t7:r0/t0 ? receive/transmit data bits reading address $003d accesses th e read-only received data bits, r7:r0. writing to addr ess $003d writes the da ta to be transmitted, t7:t0. reset has no effect on the sci data register. 14.8.7 sci baud rate register the baud rate register selects the bau d rate for both th e receiver and the transmitter. scp1 and scp0 ? sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 14-5 . reset clears scp1 and scp0. address: $003d bit 7654321bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 14-13. sci data register (scdr) address: $003e bit 7654321bit 0 read: scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented r = reserved for factory test figure 14-14. sci baud ra te register (scbr) serial communications interface module (sci) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor serial communications interface module (sci) 315 non-disclosure agreement required scr2?scr0 ? sci baud rate select bits these read/write bits select the sc i baud rate divisor as shown in table 14-6 . reset clears scr2?scr0. use this formula to calc ulate the sci baud rate: where: f bus = bus frequency pd = prescaler divisor bd = baud rate divisor table 14-7 shows the sci baud rates that can be generated with a 4.9152-mhz crystal. table 14-5. sci baud rate prescaling scp1:scp0 prescaler divisor (pd) 00 1 01 3 10 4 11 13 table 14-6. sci baud rate selection scr2:scr1:scr0 baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate f bus 64 pd bd --------------------- --------------- = non-disclosure agreement required serial communications interface module (sci) technical data MC68HC708MP16 ? rev. 3.1 316 serial communications interface module (sci) freescale semiconductor table 14-7. sci baud ra te selection examples scp1:scp0 prescaler divisor (pd) scr2:scr1:scr0 baud rate divisor (bd) baud rate (f bus = 4.9152 mhz) 00 1 000 1 76,800 00 1 001 2 38,400 00 1 010 4 19,200 00 1 011 8 9600 00 1 100 16 4800 00 1 101 32 2400 00 1 110 64 1200 00 1 111 128 600 01 3 000 1 25,600 01 3 001 2 12,800 01 3 010 4 6400 01 3 011 8 3200 01 3 100 16 1600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19,200 10 4 001 2 9600 10 4 010 4 4800 10 4 011 8 2400 10 4 100 16 1200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5908 11 13 001 2 2954 11 13 010 4 1478 11 13 011 8 738 11 13 100 16 370 11 13 101 32 184 11 13 110 64 92 11 13 111 128 46 MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor input/output (i/o) ports 317 non-disclosure agreement required technical data ? MC68HC708MP16 section 15. input/output (i/o) ports 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 15.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 15.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 15.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 320 15.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 15.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 15.4.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . 322 15.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 15.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 15.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . 325 15.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 15.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 15.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 15.7.2 data direction register e . . . . . . . . . . . . . . . . . . . . . . . . . 329 15.8 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 15.8.1 port f data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 15.8.2 data direction register f . . . . . . . . . . . . . . . . . . . . . . . . . 331 non-disclosure agreement required input/output (i/o) ports technical data MC68HC708MP16 ? rev. 3.1 318 input/output (i/o) ports freescale semiconductor 15.2 introduction thirty-seven bidirectional input-output (i/o) pins and seven input pins form eight paralle l ports. all i/o pins are pr ogrammable as inputs or outputs. note: connect any unused i/o pins to an appr opriate logic level, either v dd or v ss . although the i/o ports do not require te rmination for proper operation, termination reduces e xcess current consumption and the possibility of el ectrostatic damage. addr. name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 port e data register (pte) read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0005 port f data register (ptf) read: 0 0 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset = unimplemented figure 15-1. i/o port register summary input/output (i/o) ports MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor input/output (i/o) ports 319 non-disclosure agreement required $0006 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 0 0 0 0 0 0 0 $0007 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 0 0 0 0 0 0 0 0 $0008 data direction register c (ddrc) read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 0 0 0 0 0 0 0 0 $000a data direction register e (ddre) read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 0 0 0 0 0 0 0 0 $000b data direction register f (ddrf) read: 0 0 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset: 0 0 0 0 0 0 0 0 addr. name bit 7 6 5 4 3 2 1 bit 0 = unimplemented figure 15-1. i/o port regi ster summary (continued) non-disclosure agreement required input/output (i/o) ports technical data MC68HC708MP16 ? rev. 3.1 320 input/output (i/o) ports freescale semiconductor 15.3 port a port a is an 8-bit general-pur pose bidirectional i/o port. 15.3.1 port a data register the port a data register (p ta) contains a data latch for each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. 15.3.2 data direction register a data direction register a (ddra) dete rmines whether each port a pin is an input or an output. wr iting a logic 1 to a d dra bit enables the output buffer for the corresponding port a pi n; a logic 0 dis ables the output buffer. address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset figure 15-2. port a data register (pta) address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 15-3. data direct ion register a (ddra) input/output (i/o) ports MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor input/output (i/o) ports 321 non-disclosure agreement required ddra[7:0] ? data dire ction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pi ns by writing to the port a data register before changing data direction regist er a bits fr om 0 to 1. figure 15-4 shows the port a i/o logic. figure 15-4. port a i/o circuit when bit ddrax is a l ogic 1, reading address $0000 reads the ptax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 15-1 summarizes the operation of the port a pins. table 15-1. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddra[7:0] pin pta[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddra[7:0] pta[7:0] pta[7:0] read ddra ($0006) write ddra ($0006) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus non-disclosure agreement required input/output (i/o) ports technical data MC68HC708MP16 ? rev. 3.1 322 input/output (i/o) ports freescale semiconductor 15.4 port b port b is an 8-bit general -purpose bidirectional i/o port that shares its pins with the analog-to-di gital convertor module (adc). 15.4.1 port b data register the port b data register (p tb) contains a data latch for each of the eight port b pins. ptb[7:0] ? port b data bits these read/write bits are software-p rogrammable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. 15.4.2 data direction register b data direction register b (ddrb) dete rmines whether each port b pin is an input or an output. wr iting a logic 1 to a d drb bit enables the output buffer for the corresponding port b pi n; a logic 0 dis ables the output buffer. address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset figure 15-5. port b da ta register (ptb) address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 15-6. data direct ion register b (ddrb) input/output (i/o) ports MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor input/output (i/o) ports 323 non-disclosure agreement required ddrb[7:0] ? data dire ction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pi ns by writing to the port b data register before changing data direction regist er b bits fr om 0 to 1. figure 15-7 shows the port b i/o logic. figure 15-7. port b i/o circuit when bit ddrbx is a l ogic 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 15-2 summarizes the operation of the port b pins. table 15-2. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrb[7:0] pin ptb[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrb[7:0] ptb[7:0] ptb[7:0] read ddrb ($0007) write ddrb ($0007) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus non-disclosure agreement required input/output (i/o) ports technical data MC68HC708MP16 ? rev. 3.1 324 input/output (i/o) ports freescale semiconductor 15.5 port c port c is a 7-bit general-p urpose bidirectional i/o po rt that shares two of its pins with the analog-to-dig ital convertor module (adc). 15.5.1 port c data register the port c data register (ptc) contains a data latch for each of the seven port c pins. ptc[6:0] ? port c data bits these read/write bits are software-p rogrammable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. address: $0002 bit 7654321bit 0 read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset = unimplemented figure 15-8. port c da ta register (ptc) input/output (i/o) ports MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor input/output (i/o) ports 325 non-disclosure agreement required 15.5.2 data direction register c data direction register c (ddrc) determines whet her each port c pin is an input or an output. writ ing a logic 1 to a dd rc bit enables the output buffer for the corresponding port c pi n; a logic 0 dis ables the output buffer. ddrc[6:0] ? data dire ction register c bits these read/write bits control port c data direction. reset clears ddrc[6:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writ ing to the port c dat a register before changing data direction regist er c bits fr om 0 to 1. figure 15-10 shows the port c i/o logic. figure 15-10. port c i/o circuit address: $0006 bit 7654321bit 0 read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 = unimplemented figure 15-9. data direct ion register c (ddrc) read ddrc ($0008) write ddrc ($0008) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus non-disclosure agreement required input/output (i/o) ports technical data MC68HC708MP16 ? rev. 3.1 326 input/output (i/o) ports freescale semiconductor when bit ddrcx is a l ogic 1, reading address $0002 reads the ptcx data latch. when bit ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 15-3 summarizes the operation of the port c pins. 15.6 port d port d is a 7-bit input onl y port that shares its pi ns with the pulse width modulator for motor control module (pwmmc). the port d data register (ptd) contains a data latch for each of the seven port pins. ptd[6:0] ? port d data bits these read/write bits are software programmable. reset has no effect on port d data. table 15-3. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrc[6:0] pin ptc[6:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrc[6:0] ptc[6:0] ptc[6:0] address: $0003 bit 7654321bit 0 read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset = unimplemented figure 15-11. port d da ta register (ptd) input/output (i/o) ports MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor input/output (i/o) ports 327 non-disclosure agreement required figure 15-12 shows the port d input logic. figure 15-12. port d input circuit reading address $0003 reads the voltage level on the pin. table 15-1 summarizes the operation of the port d pins. table 15-4. port d pin functions ptd bit pin mode accesses to ptd read write x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance pin ptd[6:0] (3) 3. writing affects data regist er, but does not affect input. read ptd ($0003) ptdx internal data bus non-disclosure agreement required input/output (i/o) ports technical data MC68HC708MP16 ? rev. 3.1 328 input/output (i/o) ports freescale semiconductor 15.7 port e port e is an 8-bit special function port that shares three of its pins with the timer a interface modul e (tima) and five of its pins with the timer b interface module (timb). 15.7.1 port e data register the port e data register (p te) contains a data latch for each of the eight port e pins. pte[7:0] ? port e data bits pte[7:0] are read/write, software- programmable bits. data direction of each port e pin is under the control of the co rresponding bit in data direction register e. note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the tima or timb. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. address: $0003 bit 7654321bit 0 read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset figure 15-13. port e da ta register (pte) input/output (i/o) ports MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor input/output (i/o) ports 329 non-disclosure agreement required 15.7.2 data direction register e data direction register e (ddre) dete rmines whether each port e pin is an input or an output. wr iting a logic 1 to a d dre bit enables the output buffer for the corresponding port e pi n; a logic 0 dis ables the output buffer. ddre[7:0] ? data dire ction register e bits these read/write bits control port e data direction. reset clears ddre[7:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note: avoid glitches on port e pi ns by writing to the port e data register before changing data direction regist er e bits fr om 0 to 1. figure 15-15 shows the port e i/o logic. figure 15-15. port e i/o circuit address: $000a bit 7654321bit 0 read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 figure 15-14. data direct ion register e (ddre) read ddre ($000a) write ddre ($000a) reset write pte ($0004) read pte ($0004) ptex ddrex ptex internal data bus non-disclosure agreement required input/output (i/o) ports technical data MC68HC708MP16 ? rev. 3.1 330 input/output (i/o) ports freescale semiconductor when bit ddrex is a l ogic 1, reading address $0004 reads the ptex data latch. when bit ddrex is a logic 0, reading address $0004 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 15-3 summarizes the operation of the port e pins. 15.8 port f port f is a 6-bit special function port that shares f our of its pins with the serial peripheral interface module (s pi) and two pins with the serial communications interface (sci). 15.8.1 port f data register the port f data register (p tf) contains a data latc h for each of the six port f pins. table 15-5. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddre[7:0] pin pte[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddre[7:0] pte[7:0] pte[7:0] address: $0005 bit 7654321bit 0 read: 0 0 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset = unimplemented figure 15-16. port f da ta register (ptf) input/output (i/o) ports MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor input/output (i/o) ports 331 non-disclosure agreement required ptf[5:0] ? port f data bits these read/write bits are software programmable. data direction of each port f pin is under the control of the correspondi ng bit in data direction register f. rese t has no effect on ptf[5:0]. note: data direction register f (ddrf) does not affect th e data direction of port f pins that are being used by the spi or sci module. however, the ddrf bits always determine whether reading port f retu rns the states of the latches or the states of the pins. 15.8.2 data direction register f data direction register f (ddrf) det ermines whether each port f pin is an input or an output. writing a logic 1 to a ddrf bit enables the output buffer for the corresponding port f pi n; a logic 0 dis ables the output buffer. ddrf[5:0] ? data direction register f bits these read/write bits control port f data direction. reset clears ddrf[5:0], configuring a ll port f pins as inputs. 1 = corresponding port f pi n configured as output 0 = corresponding port f pi n configured as input note: avoid glitches on port f pins by writ ing to the port f dat a register before changing data direction regist er f bits from 0 to 1. figure 15-18 shows the port f i/o logic. address: $0005 bit 7654321bit 0 read: 0 0 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset: 000000 = unimplemented figure 15-17. data dir ect register f (ddrf) non-disclosure agreement required input/output (i/o) ports technical data MC68HC708MP16 ? rev. 3.1 332 input/output (i/o) ports freescale semiconductor figure 15-18. port f i/o circuit when bit ddrfx is a l ogic 1, reading address $0005 reads the ptfx data latch. when bit dd rfx is a logic 0, r eading address $0005 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 15-3 summarizes the operation of the port f pins. table 15-6. port f pin functions ddrf bit ptf bit i/o pin mode accesses to ddrf accesses to ptf read/write read write 0x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrf[6:0] pin ptf[6:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrf[6:0] ptf[6:0] ptf[6:0] read ddrf ($000b) write ddrf ($000b) reset write ptf ($0005) read ptf ($0005) ptfx ddrfx ptfx internal data bus MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor computer operating properly (cop) 333 non-disclosure agreement required technical data ? MC68HC708MP16 section 16. computer operating properly (cop) 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 16.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.4.1 cgmxclk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.4.2 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.4.3 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16.4.4 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 16.4.5 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 16.4.6 copd (cop disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 16.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 16.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 16.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 16.8 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 16.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 337 16.2 introduction this section describes the computer operating properly module (cop, version b), a free-running counter that generates a reset if allowed to overflow. the cop module helps softw are recover from runaway code. prevent a cop reset by periodically clearing the cop counter. non-disclosure agreement required computer operating properly (cop) technical data MC68HC708MP16 ? rev. 3.1 334 computer operating properly (cop) freescale semiconductor 16.3 functional description figure 16-1 shows the structure of the cop module. figure 16-1. cop block diagram copctl write cgmxclk reset vector fetch sim reset circuit sim reset status register internal reset sources (1) sim clear bits 12?4 13-bit sim counter clear all bits 6-bit cop counter copd (from config) reset copctl write clear cop module copen (from sim) cop counter note: see 7.4.2 active resets from internal sources . addr. name bit 7 6 5 4 3 2 1 bit 0 $ffff cop control register (copctl) read: low byte of reset vector write: writing to $ffff clears cop counter reset: unaffected by reset figure 16-2. cop i/o register summary computer operating properly (cop) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor computer operating properly (cop) 335 non-disclosure agreement required the cop counter is a fr ee-running 6-bit counter preceded by the 13-bit system integration module (sim) counter. if not cl eared by software, the cop counter overflows and generates an asynchronous reset after 2 18 ?2 4 cgmxclk cycles. with a 4.9152 -mhz crystal, the cop timeout period is 53.3 ms. writing any value to location $ffff before overflow occurs clears the cop c ounter and prevents reset. a cop reset pulls the rst pin low for 32 cgm xclk cycles and sets the cop bit in the sim reset st atus register (srsr) (see 7.7.3 sim reset status register ). note: place cop clearing instructions in the main program and not in an interrupt subroutine. su ch an interrupt subrout ine could keep the cop from generating a reset even while the main pr ogram is not working properly. 16.4 i/o signals the following paragraphs descri be the signals shown in figure 16-1 . 16.4.1 cgmxclk cgmxclk is the crystal oscillator output si gnal. cgmxclk frequency is equal to the crystal frequency. 16.4.2 copctl write writing any value to the cop c ontrol register (copctl) (see 16.5 cop control register ) clears the cop counter a nd clears bits 12 through 4 of the sim counter. readi ng the cop control register returns the reset vector. 16.4.3 power-on reset the power-on reset (por) ci rcuit in the sim clears the sim counter 4096 cgmxclk cycles after power-up. non-disclosure agreement required computer operating properly (cop) technical data MC68HC708MP16 ? rev. 3.1 336 computer operating properly (cop) freescale semiconductor 16.4.4 internal reset an internal reset clears the sim counter and the cop counter. 16.4.5 reset vector fetch a reset vector fetch occurs when the vector addres s appears on the data bus. a reset vector fetch clears the sim counter. 16.4.6 copd (cop disable) the copd signal reflec ts the state of the cop di sable bit (copd) in the configuration regist er (config). (see section 5. configuration register (config) .) 16.5 cop control register the cop control register is locat ed at address $ffff and overlaps the reset vector. writing any value to $ffff clears t he cop counter and starts a new timeout per iod. reading location $ffff returns the low byte of the reset vector. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: writing to $ffff clears cop counter reset: unaffected by reset figure 16-3. cop cont rol register (copctl) computer operating properly (cop) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor computer operating properly (cop) 337 non-disclosure agreement required 16.6 interrupts the cop does not generate cpu interrupt requests. 16.7 monitor mode the cop is disabled in monitor mode when v dd +v hi is present on the irq1 /v pp pin or on the rst pin. 16.8 wait mode the wait instruction puts the mcu in low-power-consumption standby mode. the cop continues to oper ate during wait mode. 16.9 cop module during break mode the cop is disabled during a break interrupt when v dd +v hi is present on the rst pin. non-disclosure agreement required computer operating properly (cop) technical data MC68HC708MP16 ? rev. 3.1 338 computer operating properly (cop) freescale semiconductor MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor external interrupt (irq) 339 non-disclosure agreement required technical data ? MC68HC708MP16 section 17. external interrupt (irq) 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 17.5 irq1 /v pp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343 17.6 irq module during break mode. . . . . . . . . . . . . . . . . . . . . . . 344 17.7 irq status and control register . . . . . . . . . . . . . . . . . . . . . . 345 17.2 introduction this section describes t he external interrupt module (irqepm, version b), which supports exter nal interrupt functions. 17.3 features features of the irq module include: a dedicated external interrupt pin (irq1 /v pp ) hysteresis buffers non-disclosure agreement required external interrupt (irq) technical data MC68HC708MP16 ? rev. 3.1 340 external interrupt (irq) freescale semiconductor 17.4 functional description a logic 0 applied to any of the external interrupt pins can latch a cpu interrupt request. figure 17-1 shows the structur e of the irq module. interrupt signals on the irq1 /v pp pin are latched into the irq1 latch. an interrupt latch remains set until on e of the following actions occurs: vector fetch ? a vector fetch au tomatically generates an interrupt acknowledge signal that clears t he latch that caused the vector fetch. software clear ? software can clear an interrupt latch by writing to the appropriate ackn owledge bit in the in terrupt status and control register (iscr). writing a logic 1 to the a ck1 bit clears the irq1 latch. reset ? a reset automatically clears both interrupt latches. figure 17-1. irq module block diagram ack1 imask1 dq ck clr irq1 high interrupt to mode select logic irq1 latch request irq1 /v pp v dd mode1 voltage detect synchro- nizer addr. name bit 7 6 5 4 3 2 1 bit 0 $001e irq status and control register (iscr) read: 0 0 0 0 irq1f 0 imask1 mode1 write: ack1 reset: 0 0 0 0 0 0 0 0 figure 17-2. irq i/o register summary external interrupt (irq) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor external interrupt (irq) 341 non-disclosure agreement required the external interrupt pins are fa lling-edge-triggered and are software- configurable to be both falling- edge and low-level-triggered. the mode1 bit in the iscr controls t he triggering sensit ivity of the irq1 /v pp pin. when the interrupt pin is edge-triggered only, the interr upt latch remains set until a vector fe tch, software clear, or reset occurs. when the interrupt pin is both fallin g-edge and low-leve l-triggered, the interrupt latch remains set until both of the following occur: vector fetch, software clear, or reset return of the interr upt pin to logic 1 the vector fetch or softwar e clear can occur before or after the interrupt pin returns to logic 1. as long as the pin is low, t he interrupt request remains pending. when set, the imask1 bi t in the iscr mask al l external interrupt requests. a latched interrupt request is not pres ented to the interrupt priority logic unless t he imask bit is clear. note: the interrupt mask (i) in the conditi on code register (ccr) masks all interrupt requests, including external inte rrupt requests. (see figure 17-3 .) non-disclosure agreement required external interrupt (irq) technical data MC68HC708MP16 ? rev. 3.1 342 external interrupt (irq) freescale semiconductor figure 17-3. irq interrupt flowchart from reset i bit set? fetch next yes no interrupt? instruction. swi instruction? rti instruction? no stack cpu registers. no set i bit. load pc with interrupt vector. no yes unstack cpu registers. execute instruction. yes yes external interrupt (irq) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor external interrupt (irq) 343 non-disclosure agreement required 17.5 irq1 /v pp pin a logic 0 on the irq1 /v pp pin can latch an inte rrupt request into the irq1 latch. a vector fetc h, software clear, or reset clears the irq1 latch. if the mode1 bit is set, the irq1 /v pp pin is both falling-edge-sensitive and low-level-sensitive. with mode1 set, both of the following actions must occur to clear the irq1 latch: vector fetch, software clear, or reset ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software can generate the interrupt acknowledge si gnal by writing a logic 1 to the ack1 bit in the in terrupt status and cont rol register (iscr). the ack1 bit is useful in app lications that poll the irq1 /v pp pin and require software to clear the irq1 latch. writing to the ack1 bit can also prevent spurious inte rrupts due to noi se. setting ack1 does not affect subsequent transitions on the irq1 /v pp pin. a falling edge that occurs after writ ing to the ack1 bit latches another interrupt request. if the ir q1 mask bit, imask1, is clear, the cpu loads the pr ogram counter with th e vector address at locations $fffa and $fffb. return of the irq1 /v pp pin to logic 1 ? as long as the irq1 /v pp pin is at logic 0, the irq1 latch remains set. the vector fetch or software cl ear and the return of the irq1 /v pp pin to logic 1 can occur in an y order. the interrupt re quest remains pending as long as the irq1 /v pp pin is at logic 0. if the mode1 bit is clear, the irq1 /v pp pin is falling-edge-sensitive only. with mode1 clear, a vector fetch or software clear immediately clears the irq1 latch. use the bih or bil in struction to read the logic level on the irq1 /v pp pin. note: when using the level-sensit ive interrupt trigger, av oid false interrupts by masking interrupt requests in the interrupt routine. non-disclosure agreement required external interrupt (irq) technical data MC68HC708MP16 ? rev. 3.1 344 external interrupt (irq) freescale semiconductor 17.6 irq module during break mode the system integration module (sim ) controls whether the irq1 interrupt latch can be cleared during t he break state. the bcfe bit in the sim break flag control register (s bfcr) enables softwa re to clear the latches during the break state. (see 7.7.4 sim break flag control register .) to allow software to clear the irq1 latch during a break interrupt, write a logic 1 to the bcf e bit. if a latch is cleared during the break state, it remains cleared when the m cu exits the break state. to protect the latches during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writing to t he ack1 bit in the irq status and control regi ster during the break state has no effect on the irq latches. (see 17.7 irq status a nd control register .) external interrupt (irq) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor external interrupt (irq) 345 non-disclosure agreement required 17.7 irq status and control register the irq status and control register (iscr) has t hese functions: clears the irq1 interrupt latch masks irq1 interrupt requests controls triggering se nsitivity of the irq1 /v pp interrupt pin ack1 ? irq1 interrupt request acknowledge bit writing a logic 1 to th is write-only bit clears the irq1 latch. ack1 always reads as logic 0. reset clears ack1. imask1 ? irq1 interrupt mask bit writing a logic 1 to this read/write bit disables irq1 interrupt requests. reset clears imask1. 1 = irq1 interrupt requests disabled 0 = irq1 interrupt requests enabled mode1 ? irq1 edge/level select bit this read/write bit cont rols the triggering se nsitivity of the irq1 /v pp pin. reset clears mode1. 1 = irq1 /v pp interrupt requests on falling edges and low levels 0 = irq1 /v pp interrupt requests on falling edges only irq1f ? irq1 flag this read-only bit acts as a status flag, indicating an irq1 event occurred. 1 = external irq1 event occurred 0 = external irq1 event did not occur address: $001e read: 0000 irq1f 0 imask1 mode1 write: ack1 reset:00000000 = unimplemented figure 17-4. irq status and control register (iscr) non-disclosure agreement required external interrupt (irq) technical data MC68HC708MP16 ? rev. 3.1 346 external interrupt (irq) freescale semiconductor MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor low-voltage inhibit (lvi) 347 non-disclosure agreement required technical data ? MC68HC708MP16 section 18. low-voltage inhibit (lvi) 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348 18.4.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 18.4.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . 349 18.4.3 false reset protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 18.5 lvi status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 18.6 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351 18.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 18.2 introduction this section describes t he low-voltage inhibit module (lvi47, version a), which monitors the voltage on the v dd pin and can fo rce a reset when the v dd voltage falls to the lvi trip voltage. 18.3 features features of the lvi module include: programmable lvi reset programmable power consumption digital filtering of v dd pin level non-disclosure agreement required low-voltage inhibit (lvi) technical data MC68HC708MP16 ? rev. 3.1 348 low-voltage inhibit (lvi) freescale semiconductor 18.4 functional description figure 18-1 shows the structur e of the lvi module. the lvi is enabled out of reset. the lvi module cont ains a bandgap reference circuit and comparator. the lvi power bit, lvipwr, enables the lvi to monitor v dd voltage. the lvi reset bit, lvirst, enables the lvi module to generate a reset when v dd falls below a voltage, lvi tripf , and remains at or below that level for nine or more consecutive cpu cycles. lvipwr and lvirst are in the configurat ion register (config). (see section 5. configuration register (config) .) once an lvi reset occurs, the mcu remains in reset until v dd rises above a voltage, lvi tripr . v dd must be above lvi tripr for only one cpu cycle to bring the mcu out of reset. (see 7.4.2.5 low-voltage inhibit (lvi) reset .) the output of the comparator controls the state of t he lviout flag in the lvi status register (lvisr). an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices. figure 18-1. lvi module block diagram low v dd lvirst v dd > lvi trip = 0 v dd < lvi trip = 1 lviout lvipwr detector v dd lvi reset from config from config v dd digital filter cpu clock anlgtrip low-voltage inhibit (lvi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor low-voltage inhibit (lvi) 349 non-disclosure agreement required 18.4.1 polled lvi operation in applications that can operate at v dd levels below the lvi tripf level, software can monitor v dd by polling the lviout bi t. in the configuration register, the lvipwr bit must be at l ogic 0 to enable t he lvi module, and the lvirst bit must be at logic 1 to disable lvi resets. 18.4.2 forced reset operation in applications that require v dd to remain above the lvi tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls to the lvi tripf level and remains at or bel ow that level for nine or more consecutive cpu cycles. in the configuration regi ster, the lvipwr and lvirst bits must be at logic 0 to enable the lvi module and to enable lvi resets. 18.4.3 false reset protection the v dd pin level is digitally filtered to reduce false resets due to power supply noise. in order for the lvi module to reset the mcu,v dd must remain at or below the lvi tripf level for nine or more consecutive cpu cycles. v dd must be above lvi tripr for only one cpu cycle to bring the mcu out of reset. addr. name bit 7 6 5 4 3 2 1 bit 0 $fe0f lvi status register (lvisr) read: lviout 0 0 0 0 0 0 0 write: reset: 0 0 0 0 0 0 0 0 = unimplemented figure 18-2. lvi i/ o register summary non-disclosure agreement required low-voltage inhibit (lvi) technical data MC68HC708MP16 ? rev. 3.1 350 low-voltage inhibit (lvi) freescale semiconductor 18.5 lvi status register the lvi status regist er (lvisr) flags v dd voltages below the lvi tripf level . lviout ? lvi output bit this read-only flag be comes set when the v dd voltage falls below the lvi tripf voltage for 32 to 40 cgmxclk cycles. (see table 18-1 .) reset clears the lviout bit. address: $fe0f bit 7654321bit 0 read: lviout 0000000 write: reset:00000000 = unimplemented figure 18-3. lvi stat us register (lvisr) table 18-1. lviout bit indication v dd lviout at level: for number of cgmxclk cycles: v dd > lvi tripr any 0 v dd < lv i tripf < 32 cgmxclk cycles 0 v dd < lv i tripf between 32 & 40 cgmxclk cycles 0 or 1 v dd < lv i tripf > 40 cgmxclk cycles 1 lv i tripf < v dd < lv i tripr any previous value low-voltage inhibit (lvi) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor low-voltage inhibit (lvi) 351 non-disclosure agreement required 18.6 lvi interrupts the lvi module does not gener ate interrupt requests. 18.7 wait mode the wait instruction puts the mcu in low-power-consumption standby mode. with the lvipwr bit in the configuration register programmed to logic 0, the lvi module is active after a wait instruction. with the lvirst bit in the configurat ion register program med to logic 0, the lvi module c an generate a reset and bring the mcu out of wait mode. non-disclosure agreement required low-voltage inhibit (lvi) technical data MC68HC708MP16 ? rev. 3.1 352 low-voltage inhibit (lvi) freescale semiconductor MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter (adc) 353 non-disclosure agreement required technical data ? MC68HC708MP16 section 19. analog-to-digital converter (adc) 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 19.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 19.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 19.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 19.4.4 continous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 19.4.5 accuracy and precision. . . . . . . . . . . . . . . . . . . . . . . . . . .357 19.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 19.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 19.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 19.7.1 adc analog power pin (v ddad ) . . . . . . . . . . . . . . . . . . . .358 19.7.2 adc analog ground pin (v ssad ) . . . . . . . . . . . . . . . . . . . 358 19.7.3 adc voltage reference pin (v ddaref ) . . . . . . . . . . . . . . 358 19.7.4 adc voltage decoup ling capacitor pin (v adcap ) . . . . . . 358 19.7.5 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . 359 19.7.6 adc voltage in ( advin) . . . . . . . . . . . . . . . . . . . . . . . . . . 359 19.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 19.8.1 adc status and control register . . . . . . . . . . . . . . . . . . . 360 19.8.2 adc data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363 19.8.3 adc clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 non-disclosure agreement required analog-to-digital converter (adc) technical data MC68HC708MP16 ? rev. 3.1 354 analog-to-digital converter (adc) freescale semiconductor 19.2 introduction this section describes th e analog-to-digital conv ertor. the adc is an 8-bit analog-to-dig ital convertor. 19.3 features features of the ad c module include: 10 channels with multiplexed input linear successive approximation 8-bit resolution single or continous conversion conversion complete flag or conversion complete interrupt selectable adc clock 19.4 functional description ten adc channels are availa ble for sampling extern al sources at pins ptc1/atd9:ptc0/atd8 and ptb7/a td7:ptb0/atd0. an analog multiplexer allows the single adc conv erter to select one of the 10 adc channels as adc voltage in (adcvin). adcvin is converted by the successive approximation register based counter. when the conversion is completed, the adc places the result in the adc data register and sets a flag or generates an interrupt. (see figure 19-1.) note: dma section and associat ed functions are only va lid if the mcu has a dma module. analog-to-digital converter (adc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter (adc) 355 non-disclosure agreement required figure 19-1. adc block diagram internal data bus read ddrb/ddrc write ddrb/ddrc reset write ptb/ptc read ptb/ptc ptb/cx ddrbx/ddrcx ptbx/ptcx interrupt logic channel select adc clock generator conversion complete adc voltage in (advin) adc clock cgmxclk bus clock adch[4:0] adc data register adiv[2:0] adiclk aien coco/idmas disable disable (adc channel x) non-disclosure agreement required analog-to-digital converter (adc) technical data MC68HC708MP16 ? rev. 3.1 356 analog-to-digital converter (adc) freescale semiconductor 19.4.1 adc port i/o pins ptc1/atd9:ptc0/atd8 and ptb7/a td7:ptb0/atd0 are general- purpose i/o pins that are shared with the adc channels. the channel select bits define whic h adc channel/por t pin will be used as the input signal. the a dc overrides the port i/o logic by forcing that pin as input to the adc. the rema ining adc channel s/port pins are controlled by the port i/o logic and c an be used as general-purpose i/o. writes to the port register or ddr will not have any affect on the port pin that is selected by the ad c. read of a port pin which is in use by the adc will return a logic 0. 19.4.2 voltage conversion when the input voltage to the adc equals v ddad , the adc converts the signal to $ff (full scale). if the input voltage equals v ssad, the adc converts it to $00. input voltages between v ddad and v ssad are straight- line linear conversions. all other input volt ages will result in $ff if greater than v ddad and $00 if less than v ssad . note: input voltage should not exceed the analog supply voltages. 19.4.3 conversion time conversion starts after a write to the adscr. conversion time in terms of the number of bus cycles is a function of oscillator frequency, bus frequency, and adiv prescaler bits. for example, with an oscillator frequency of 8 mhz, a bus frequen cy of 4 mhz, and an adc clock frequency of 1 mhz, one conversion will take betw een 16 adc and 17 adc clock cycles or between 16 and 17 s. there will be 128 bus cycles between each conversion. sample rate is approximately 30 khz. 16-17 adc cycles conversion time = adc frequency number of bus cycles = co nversion time x bus frequency analog-to-digital converter (adc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter (adc) 357 non-disclosure agreement required 19.4.4 continous conversion in the continuous conver sion mode, the adc data r egister will be filled with new data after each conversion. data from the previous conversion will be overwritten whether that dat a has been read or not. conversions will continue until the adco bit is cleared. the coco bit is set after the first conversion and will stay set for the next several conversions until the next write of the adc status and contro l register or the next read of the adc data register. 19.4.5 accuracy and precision the conversion process is monot onic and has no missing codes. 19.5 interrupts when the aien bit is set, the adc m odule is capable of generating either cpu or dma interrupt after each adc conversion. a cpu interrupt is generated if the coco/i dmas bit is at l ogic 0. if coco/idmas bit is set, a dma interrupt is genera ted. the coco/idmas bi t is not used as a conversion complete flag when interrupts are enabled. 19.6 wait mode the wait instruction can put the mcu in low-power-consumption standby mode. the adc continues norma l operation during wait mode. any enabled cpu interrupt request fro m the adc can bring t he mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by se tting adch[4:0] bits in the adc status and control register before exec uting the wait instruction. non-disclosure agreement required analog-to-digital converter (adc) technical data MC68HC708MP16 ? rev. 3.1 358 analog-to-digital converter (adc) freescale semiconductor 19.7 i/o signals the adc module has 10 i/ o signals that are sh ared with port b and port c. 19.7.1 adc analog power pin (v ddad ) the adc analog portion uses v ddad as its power pin. connect the v ddad pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v ddad for good results. note: route v ddad carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 19.7.2 adc analog ground pin (v ssad ) the adc analog portion uses v ssad as its ground pi n. connect the v ssad pin to the same voltage potential as v ss . 19.7.3 adc voltage reference pin (v ddaref ) v ddaref is the power supply for se tting the reference voltage v refh . connect the v ddaref pin to the same voltage potential as v dda . 19.7.4 adc voltage decoupling capacitor pin (v adcap ) v adcap is one of two reference supp lies and is gener ated from v ddaref with a value (v ddaref ) /2. place a bypass capac itor on this pin to decouple noise. v adcap pin can also be used to drive an upper reference value of (v ddaref ) /2 with an exter nal voltage reference. analog-to-digital converter (adc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter (adc) 359 non-disclosure agreement required 19.7.5 adc voltage reference low pin (v refl ) v refl is the lower reference supp ly for the adc. connect the v refl pin to the same voltage potential as v ssad . 19.7.6 adc voltage in (advin) advin is the input vo ltage signal from one of t he 10 adc channels to the adc module. 19.8 i/o registers the following i/o registers control and monitor operati on of the adc: adc status and cont rol register (adscr) adc data register (adr) adc clock register (adclk) non-disclosure agreement required analog-to-digital converter (adc) technical data MC68HC708MP16 ? rev. 3.1 360 analog-to-digital converter (adc) freescale semiconductor 19.8.1 adc status and control register these paragraphs describe the function of the adc status and control register (adscr). coco/idmas ? c onversions complete / interrupt dma select when aien bit is a logic 0, the co co/idmas is a r ead-only bit which is set each time a conversion is co mpleted except in the continous conversion mode where it is set after the first c onversion. this bit is cleared whenever the adc status and control regi ster is written or whenever the adc data register is read. if aien bit is a logic 1, the coco/idmas is a read/write bit which selects either cpu or dma to se rvice the adc interrupt request. reset clears this bit. 1 = conversion completed (aien = 0)/dma interrrupt (aien = 1) 0 = conversion not completed (aie n = 0)/cpu interrupt (aien = 1) aien ? adc interrupt enable when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cl eared when the dat a register is read or the status/control register is written. re set clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled address: $0017 bit 7654321bit 0 read: coco/ idmas aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00000000 figure 19-2. adc status and contro l register (adscr) analog-to-digital converter (adc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter (adc) 361 non-disclosure agreement required adco ? adc continuous conversion when set, the adc will convert sa mples continuously and update the adr register at the end of each conversion. only one conversion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch[4:]0 ? adc channel select bits adch4, adch3, adch2, adch1, and adch0 fo rm a 5-bit field which is used to sele ct one of 14 adc chann els. the 14 channels are detailed in table 19-1 . take care to prevent switching noise from corrupting the analog signal when simultaneously using a port pin as both an analog and digital input. (see table 19-1.) the adc subsystem is turned off w hen the channel select bits are all set to one. this feature allows fo r reduced power consumption for the mcu when the adc is not used. note: recovery from the disabled stat e requires one conversion cycle to stabilize. the voltage levels suppl ied from internal reference nodes as specified in table 19-1 are used to verify the operation of the adc converter both in production te st and for user applications. non-disclosure agreement required analog-to-digital converter (adc) technical data MC68HC708MP16 ? rev. 3.1 362 analog-to-digital converter (adc) freescale semiconductor table 19-1. mux channel select adch4 adch3 adch2 adch1 adch0 input select 00000 ptb0/atd0 00001 ptb1/atd1 00010 ptb2/atd2 00011 ptb3/atd3 00100 ptb4/atd4 00101 ptb5/atd5 00110 ptb6/atd6 00111 ptb7/atd7 01000 ptc0/atd8 01001 ptc1/atd9 01010 unused (2) 01011 ? 01100 ? 01101 ? 01110 ? 01111 ? 10000 11010 unused (1) 11011 reserved (2) 1 1 1 0 0 2*v adcap 1 1 1 0 1 v adcap 1 1 1 1 0 2*v refl 1 1 1 1 1 [adc power off] notes: 1. if any unused channels are selected, t he resulting adc conversion will be unknown. 2. used for factory testing. analog-to-digital converter (adc) MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor analog-to-digital converter (adc) 363 non-disclosure agreement required 19.8.2 adc data register one 8-bit result register is provi ded. this register is updated each time an adc conversion completes. 19.8.3 adc clock register this register selects the clock frequency for the adc. adiv2:adiv0 ? adc cl ock prescaler bits adiv2, adiv1, and adiv0 form a 3-bit field wh ich selects the divide ratio used by the a dc to generate the in ternal adc clock. table 19-2 shows the available clock configurations. the adc clock should be set to 1 mhz. address: $0019 bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset:00000000 = unimplemented figure 19-3. adc data register (adr) address: $001a bit 7654321bit 0 read: adiv2 adiv1 adiv0 adclk 0000 write: reset:00000000 = unimplemented figure 19-4. adc clock register (adclkr) non-disclosure agreement required analog-to-digital converter (adc) technical data MC68HC708MP16 ? rev. 3.1 364 analog-to-digital converter (adc) freescale semiconductor adiclk ? adc input clock select adiclk selects either bus clock or cgmxclk as the input clock source to generate the internal adc clock. reset selects cgmxclk as the adc clock source. if the external clock (cgmxclk) is equal or great er than 1 mhz, cgmxclk can be used as the cl ock source for the adc. if cgmxclk is less than 1 mhz, use the pll-generated bus clock as the clock source. as l ong as the internal adc clock is at 1 mhz, correct operation ca n be guaranteed. (see 21.11 analog-to-digital converter (adc) characteristics .) 1 = internal bus clock 0 = external clock (cgmxclk) table 19-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock /1 0 0 1 adc input clock /2 0 1 0 adc input clock /4 0 1 1 adc input clock /8 1 x x adc input clock /16 x = don?t care cgmxclk or bus frequency 1 mhz = adiv[2:0] MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor power-on reset (por) 365 non-disclosure agreement required technical data ? MC68HC708MP16 section 20. power-on reset (por) 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 20.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365 20.2 introduction this section describes the power-on reset (por ) module (version b). 20.3 functional description the por module provides a known, st able signal to the mcu at power- on. this signal tracks v dd until the mcu generates a feedback signal to indicate that it is pro perly initialized. at this time, the por drives its output low. the por is not a brown-out detector , low-voltage detector, or glitch detector. v dd at the por must go comple tely to zero to reset the mcu. to detect pow er-loss conditions, use a low voltage inhibit module (lvi) or ot her suitable circuit. inpu ts to the por_b00 are siminit and seczdet fr om the sim and eprom security circuits, respectively. non-disclosure agreement required power-on reset (por) technical data MC68HC708MP16 ? rev. 3.1 366 power-on reset (por) freescale semiconductor figure 20-1. por block diagram v dd porlo porhi cntrclr cntrrst notes: 1. porhi goes high at power-up and is cleared when the sim sets cntrclr. 2. signal names are not necessarily accurate. this di agram is for logical illustration only and may not represent actual circuitry. MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor electrical specifications 367 non-disclosure agreement required technical data ? MC68HC708MP16 section 21. electrical specifications 21.1 contents 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 21.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 368 21.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 369 21.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 21.6 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 370 21.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 21.8 serial peripheral interface characteri stics . . . . . . . . . . . . . . . 372 21.9 timer interface module characterist ics . . . . . . . . . . . . . . . . . 375 21.10 clock generation modu le electrical characteri stics. . . . . . . . 375 21.11 analog-to-digital converter (adc) characteristics. . . . . . . . . 377 21.12 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 21.2 introduction this section contains electrical and timing specifications. these values are design targets and have no t yet been fully characterized. non-disclosure agreement required electrical specifications technical data MC68HC708MP16 ? rev. 3.1 368 electrical specifications freescale semiconductor 21.3 absolute maximum ratings maximum ratings are t he extreme limits to which the mcu can be exposed without perman ently damaging it. note: this device is not guar anteed to operate properly at the maximum ratings. refer to 21.6 dc electrical characteristics for guaranteed operating conditions. note: this device contains circ uitry to protect the i nputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applic ation of any voltage higher than maximum-rated voltages to this hi gh-impedance circui t. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are co nnected to an appropriate logic voltage level (for example, either v ss or v dd .) table 21-1. absolute maximum ratings (1) characteristic symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage v in v ss ?0.3 to v dd +0.3 v programming voltage v pp v ss ?0.3 to 14.0 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma note: 1. voltages referenced to v ss . electrical specifications MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor electrical specifications 369 non-disclosure agreement required 21.4 functional operating range 21.5 thermal characteristics table 21-2. operating range characteristic symbol value unit operating temperature range (see note) MC68HC708MP16cfu MC68HC708MP16vfu t a ?40 to 85 ?40 to 105 c operating voltage range v dd 5.0 10% v note: see freescale repres entative for temper ature availability. c = extended temperature range (?40 to +85 c ) v = automotive temperature range (?40 to +105 c ) table 21-3. thermal characteristics characteristic symbol value unit thermal resistance, qfp (64 pin) ja 76 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) k p d x (t a + 273 c ) + p d 2 x ja w/ c average junction temperature t j t a + (p d x ja ) c maximum junction temperature t jm 125 c notes: 1. power dissipation is a f unction of temperature. 2. k is a constant unique to the device. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . non-disclosure agreement required electrical specifications technical data MC68HC708MP16 ? rev. 3.1 370 electrical specifications freescale semiconductor 21.6 dc electrical characteristics table 21-4. dc electri cal characteristics (v dd = 5.0 vdc 10%) (1) characteristic symbol min typ (2) max unit output high voltage (i load = ?2.0 ma) all i/o pins v oh v dd ?0.8 ? ? v output low voltage (i load = 1.6ma) all i/o pins v ol ??0.4v pwm pin output source current (v oh = v dd ?0.8 v) i oh 7??ma pwm pin output sink current (v ol = 0.8 v) i ol ?20 ? ? ma input high voltage all ports, irqs, reset, osc1 v ih 0.7 x v dd ?v dd v input low voltage all ports, irqs, reset, osc1 v il v ss ? 0.3 x v dd v v dd supply current run (3) wait (4) quiescent (5) i dd ? ? ? ? ? ? 40 14 750 ma ma a i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf low-voltage inhibit reset v lv r 4.33 4.45 4.58 v low-voltage reset/recover hysteresis h lvr 50 100 150 mv por rearm voltage (6) *v por 0?100mv por rise time ramp rate (8) r por 0.035 ? ? v/m s notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f osc = 8.2 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configur ed as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f osc = 8.2 mhz); all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf on osc2; all ports configured as inputs; osc2 capacitance linearly affects wait i dd ; measured with pll, and lvi enabled. 5. quiescent i dd measured with pll and lvi disengaged, ocs1 grounde d, no port pins sourcing current. measured through combination of v dd , v ddad , and v dda . 6. maximum is highest voltage that por is guaranteed. 7. maximum is highest voltage that por is possible. 8. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. electrical specifications MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor electrical specifications 371 non-disclosure agreement required 21.7 control timing table 21-5. control timing (v dd = 5.0 vdc 10%) (1) characteristic symbol min max unit frequency of operation (2) crystal option external clock option (3) f osc 1 m dc (4) 8 m 32.8 m hz internal operating frequency f op ?8.2mhz reset input pulse width low (5) t irl 50 ? ns notes: 1. v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. 2. see table 21-8 and table 21-9 for more information. 3. no more than 10% duty cycle deviation from 50%. 4. some modules may require a minimum frequency greater than dc for proper operation; se e appropriate table for this information. 5. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. non-disclosure agreement required electrical specifications technical data MC68HC708MP16 ? rev. 3.1 372 electrical specifications freescale semiconductor 21.8 serial peripheral interface characteristics table 21-6. serial peripheral interface (s pi) timing (v dd = 5.0 vdc 10%) (1) diagram number (2) characteristic symbol min max unit operating frequency master slave f op(m) f op(s) f op /128 dc f op /2 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 ? t cyc 2 enable lead time t lead(s) 15 ? ns 3 enable lag time t lag(s) 15 ? ns 4 clock (sck) high time master slave t sckh(m) t sckh(s) 100 50 ? ? ns 5 clock (sck) low time master slave t sckl(m) t sckl(s) 100 50 ? ? ns 6 data setup time (inputs) master slave t su(m) t su(s) 45 5 ? ? ns 7 data hold time (inputs) master slave t h(m) t h(s) 0 15 ? ? ns 8 access time, slave (3) cpha = 0 chpa = 1 t a(cp0) t a(cp1) 0 0 40 20 ns 9 disable time, slave (4) t dis(s) ?25ns 10 data valid time (after enable edge) master slave (5) t v(m) t v(s) ? ? 10 40 ns notes: 1. all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted; assumes 100 pf load on all spi pins. 2. numbers refer to dimensions in figure 21-1 and figure 21-2 . 3. time to data active from high-impedance state. 4. hold time to high-impedance state. 5. with 100 pf on all spi pins. electrical specifications MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor electrical specifications 373 non-disclosure agreement required figure 21-1. spi master timing note ss pin of master held high. msb in ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 11 7 6 note note: this last clock edge is generated inte rnally, but is not seen at the sck pin. ss pin of master held high. msb in ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 11 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) note: this first clock edge is generated inte rnally, but is not seen at the sck pin. non-disclosure agreement required electrical specifications technical data MC68HC708MP16 ? rev. 3.1 374 electrical specifications freescale semiconductor figure 21-2. spi slave timing note: not defined but normally msb of character just received. slave ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (input) mosi (output) 4 5 5 1 4 msb in bits 6?1 8 6 10 11 11 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out note: not defined but normally lsb of character previ ously transmitted. slave ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) 4 5 5 1 4 msb in bits 6?1 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11 electrical specifications MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor electrical specifications 375 non-disclosure agreement required 21.9 timer interface module characteristics 21.10 clock generation module electrical characteristics table 21-7. tim timing characteristic symbol min max unit input capture pulse width t tih, t til 125 ? ns input clock pulse width t tch, t tcl (1/f op ) + 5 ? ns table 21-8. cgm component specifications characteristic symbol min typ max notes crystal load capacitance c l ??? consult crystal manufacturing data crystal fixed capacitance c 1 ?2*c l ? consult crystal manufacturing data crystal tuning capacitance c 2 ?2*c l ? consult crystal manufacturing data feedback bias resistor r b ?22 m ? ? series resistor r s 0330 k ? 1 m ? not required filter capacitor c f ? c fact * (v dda /f xclk ) ? bypass capacitor c byp ?0.1 f? c byp must provide low ac impedance from f = f xclk /100 to 100*f vclk , so series resistance must be considered. table 21-9. cgm o perating conditions characteristic symbol min typ max crystal reference frequency f xclk 1mhz ? 8 mhz range nominal multiplier f nom ? 4.9152 mhz ? vco center-of-range frequency f vrs 4.9152 mhz ? 32.8 mhz vco frequency multiplier n 1 ? 15 vco center of range multiplier l 1 ? 15 vco operating frequency f vclk f vrsmin ?f vrsmax non-disclosure agreement required electrical specifications technical data MC68HC708MP16 ? rev. 3.1 376 electrical specifications freescale semiconductor table 21-10. cgm acquisition /lock time specifications description symbol min typ max notes filter capacitor multiply factor c fact ?0.0154? f/sv acquisition mode time factor k acq ?0.1135? v tracking mode time factor k trk ?0.0174? v manual mode time to stable t acq ? (8*v dda )/ (f x clk *k acq) ? if c f chosen correctly. manual stable to lock time t al ? (4*v dda )/ (f x clk *k trk ) ? if c f chosen correctly. manual acquisition time t lock ?t acq +t al ? tracking mode entry frequency to l e r a n c e ? trk 0? 3.6% acquisition mode entry frequency to l e r a n c e ? acq 6.3% ? 7.2% lock entry frequency tolerance ? lock 0? 0.9% lock exit frequency tolerance ? unl 0.9% ? 1.8% reference cycles per acquisition mode measurement n acq ?32? reference cycles per tracking mode measurement n trk ?128? automatic mode time to stable t acq n acq /f xclk (8*v dda )/ (f x clk *k acq) ? if c f chosen correctly. automatic stable to lock time t al n trk /f xclk (4*v dda )/ (f x clk *k trk ) ? if c f chosen correctly. automatic lock time t lock ?t acq +t al ? pll jitter (deviation of average bus frequency over 2 ms) f j 0? (f crys ) *(0.025%) *(n/4) n = vco freq. mult. (gbnt) electrical specifications MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor electrical specifications 377 non-disclosure agreement required 21.11 analog-to-digital conv erter (adc) characteristics 21.12 memory characteristics table 21-11. adc characteristics characteristic symbol min max unit notes supply voltage v ddad 4.5 5.5 v v ddad should be tied to the same potential as v dd via separate traces. input voltages v adin 0v ddad vv adin <= v ddad resolution b ad 88bits absolute accuracy a ad ?1lsb includes quantization adc internal clock f adic 500 k 1.048 m hz t aic = 1/f adic conversion range r ad v ssad v ddad v power-up time t adpu 16 t aic cycles conversion time t adc 16 17 t aic cycles sample time t ads 5?t aic cycles monotocity m ad guaranteed zero input reading z adi 00 ? hex v adin = v ssad full-scale reading f adi ?ffhexi adin = v ddad input capacitance c adi ?30 pf not tested table 21-12. memory characteristics characteristic symbol min typ max unit eprom programming voltage v epgm 12.5 13.0 13.5 v eprom data retention time t edr ? 10.0 ? years eprom programming time t epgm ?1?ms/byte ram data retention voltage v rdr 0.7 ? ? v non-disclosure agreement required electrical specifications technical data MC68HC708MP16 ? rev. 3.1 378 electrical specifications freescale semiconductor MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor mechanical specifications 379 non-disclosure agreement required technical data ? MC68HC708MP16 section 22. mechanical specifications 22.1 contents 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 22.3 plastic quad flat pack (qfp). . . . . . . . . . . . . . . . . . . . . . . . . 380 22.2 introduction this section gives the di mensions for the 64-lead plastic quad flat pack (qfp). non-disclosure agreement required mechanical specifications technical data MC68HC708MP16 ? rev. 3.1 380 mechanical specifications freescale semiconductor 22.3 plastic quad flat pack (qfp) figure 22-1. mc68hc708m p16fu (case #840b-01) l l ?a? ?b? detail a ?d? b a s v detail a p b b d ?a?, ?b?, ?d? c ?c? e h g m m detailc seating plane datum plane 1 16 ?h? 0.01 (0.004) r detail c datum plane ?h? t u q k w x s a?b m 0.20 (0.008) d s h s a?b m 0.20 (0.008) d s c 0.05 (0.002) a?b s a?b m 0.20 (0.008) d s c 0.05 (0.002) a?b s a?b m 0.20 (0.008) d s h 48 33 s a?b m 0.02 (0.008) d s c n f j base metal 32 49 17 64 dim min max min max inches millimeters a 13.90 14.10 0.547 0.555 b 13.90 14.10 0.547 0.555 c 2.15 2.45 0.085 0.096 d 0.30 0.45 0.012 0.018 e 2.00 2.40 0.079 0.094 f 0.30 0.40 0.012 0.016 g 0.80 bsc 0.031 bsc h ??? 0.25 ??? 0.010 j 0.13 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 12.00 ref 0.472 ref m 5 10 5 10 n 0.13 0.17 0.005 0.007 p 0.40 bsc 0.016 bsc q 0 7 0 7 r 0.13 0.30 0.005 0.012 s 16.95 17.45 0.667 0.687 t 0.13 ??? 0.005 ??? u 0 ??? 0 ??? v 16.95 17.45 0.667 0.687 w 0.35 0.45 0.014 0.018 x 1.6 ref 0.063 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?h? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?a?, ?b? and ?d? to be determined at datum plane ?h?. 5. dimensions s and v to be determined at seating plane ?c?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?h?. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) per side. total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor ordering information 381 non-disclosure agreement required technical data ? MC68HC708MP16 section 23. ordering information 23.1 contents 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 23.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 23.2 introduction this section contains ordering information. 23.3 mc order numbers table 23-1. mc order numbers mc order number operating temperature range MC68HC708MP16cfu (1) MC68HC708MP16vfu 1. fu = plastic quad flat pack ?40 c to 85 c ?40 c to 105 c non-disclosure agreement required ordering information technical data MC68HC708MP16 ? rev. 3.1 382 ordering information freescale semiconductor MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor glossary 383 non-disclosure agreement required technical data ? MC68HC708MP16 glossary a ? see accumulator (a). accumulator (a) ? an 8-bit general-purpose r egister in the cpu08. the cpu08 uses the accumulator to hold operands and results of arithmetic and l ogic operations. acquisition mode ? a mode of pll op eration during star tup before the pll locks on a frequency. al so see tracking mode. address bus ? the set of wires that the cpu or dma uses to read and write memory locations. addressing mode ? the way that the c pu determines the operand address for an instruction. th e m68hc08 cpu has 16 addressing modes. alu ? see arithmetic logic unit (alu). arithmetic logic unit (alu) ? the portion of the cpu that contains the logic circuitry to perform arit hmetic, logic, and manipulation operations on operands. asynchronous ? refers to logic circuits and operations that are not synchronized by a co mmon reference signal. baud rate ? the total number of bits tr ansmitted per unit of time. bcd ? see binary-coded decimal (bcd). binary ? relating to the base 2 number system. binary number system ? the base 2 number system, having two digits, 0 and 1. binary arithmetic is convenient in digital circuit design because digital circuits have two permissible voltage levels, low and high. the binary digits 0 and 1 ca n be interpreted to correspond to the two digital voltage levels. non-disclosure agreement required glossary technical data MC68HC708MP16 ? rev. 3.1 384 glossary freescale semiconductor binary-coded decimal (bcd) ? a notation that uses 4-bit binary numbers to represent the 10 decimal digits and th at retains the same positional structure of a dec imal number. for example, 234 (decimal) = 0010 0011 0100 (bcd) bit ? a binary digit. a bi t has a value of either logic 0 or logic 1. branch instruction ? an instructi on that causes t he cpu to continue processing at a memory locati on other than the next sequential address. break module ? a module in the m68hc 08 family. the break module allows software to halt program execution at a programmable point in order to enter a background routine. breakpoint ? a number written into the break address registers of the break module. when a number appear s on the internal address bus that is the same as the number in the break address registers, the cpu executes the software interrupt instruction (swi). break interrupt ? a software interrupt caused by the appearance on the internal address bus of the same value that is written in the break address registers. bus ? a set of wires that transfers logic signals. bus clocks ? there are two bus clo cks, it12 and it23. these clocks are generated by the cgm and dist ributed throughout the mcu by the sim. the frequency of the bus cl ocks, or operat ing frequency, is f op . while the frequency of these tw o clocks is the same, the phase is different. byte ? a set of eight bits. c ? the carry/borrow bit in the condition code re gister. the cpu08 sets the carry/borrow bit wh en an addition operation produces a carry out of bit 7 of the accumu lator or when a subtra ction operation requires a borrow. some logical operations and data manipulation instructions also clear or set the carry/borro w bit (as in bit test and branch instructions and sh ifts and rotates). ccr ? see condition code register. glossary MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor glossary 385 non-disclosure agreement required central processor unit (cpu) ? the primary functi oning unit of any computer system. the cpu controls the execution of instructions. cgm ? see clock generat or module (cgm). clear ? to change a bit from logic 1 to logic 0; the opposite of set. clock ? a square wave signal used to synchronize events in a computer. clock generator module (cgm) ? a module in t he m68hc08 family. the cgm generates a base clock si gnal from which the system clocks are derived. the cgm may incl ude a crystal oscillator circuit and/or phase-locked loop (pll) circuit. comparator ? a device that compares th e magnitude of two inputs. a digital comparator defines the equality or relative differences between two binary numbers. computer operating pro perly module (cop) ? a counter module in the m68hc08 family that resets t he mcu if allow ed to overflow. condition code register (ccr) ? an 8-bit register in the cpu08 that contains the interrupt ma sk bit and five bits that indicate the results of the instruction just executed. control bit ? one bit of a regi ster manipulated by software to control the operation of the module. control unit ? one of two major units of the cpu. the control unit contains logic functions that syn chronize the machine and direct various operations. the control unit decodes instructions and generates the internal control si gnals that perform the requested operations. the outputs of the control unit driv e the execution unit, which contains the arithmetic logi c unit (alu), cpu registers, and bus interface. cop ? see computer operati ng properly module (cop). counter clock ? the input clock to the ti m counter. this clock is an output of the prescale r sub-module. the freque ncy of the counter clock is f tcnt , and the period is t tcnt . cpu ? see central pr ocessor unit (cpu). non-disclosure agreement required glossary technical data MC68HC708MP16 ? rev. 3.1 386 glossary freescale semiconductor cpu08 ? the central processor unit of the m68hc08 family. cpu cycles ? a cpu clock cycle is one per iod of the internal bus-rate clock, f op , normally derived by dividing a crystal os cillator source by two or more so the high and low times wil l be equal. the length of time required to execut e an instruction is m easured in cpu clock cycles. cpu registers ? memory locations that ar e wired directly into the cpu logic instead of being part of the addressable memory map. the cpu always has direct access to the info rmation in these registers. the cpu registers in an m68hc08 are: a (8-bit accumulator) h:x (16-bit index register) sp (16-bit stack pointer) pc (16-bit program counter) ccr (condition code register containi ng the v, h, i, n, z, and c bits) csic ? customer-specifi ed integrated circuit cycle time ? the period of the operating frequency: t cyc =1/f op . decimal number system ? base 10 numbering system that uses the digits zero through nine. direct memory access module (dma) ? a m68hc08 family module that can perform dat a transfers between any two cpu-addressable locations without cpu intervention. for transmitting or receiving blocks of data to or from peripherals, dma tran sfers are faster and more code-efficient than cpu interrupts. dma ? see direct memory access module (dma). dma service request ? a signal from a periphe ral to the dma module that enables the dma modu le to transfer data. duty cycle ? a ratio of the amount of time the signal is on versus the time it is off. duty cycle is us ually represented by a percentage. glossary MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor glossary 387 non-disclosure agreement required eeprom ? electrically erasable, pr ogrammable, read-only memory. a non-volatile type of memory that can be electrically reprogrammed. eprom ? erasable, programmable, read -only memory. a non-volatile type of memory that can be erased by exposure to an ultraviolet light source and then reprogrammed. exception ? an event such as an interr upt or a reset that stops the sequential execution of the inst ructions in the main program. external interrupt module (irq) ? a module in th e m68hc08 family with both dedicated external interr upt pins and port pins that can be enabled as interrupt pins. fetch ? to copy data from a memory location into the accumulator. firmware ? instructions and data pr ogrammed into non-volatile memory. free-running counter ? a device that c ounts from zero to a predetermined number, t hen rolls over to zero and begins counting again. full-duplex transmission ? communication on a channel in which data can be sent and re ceived simultaneously. h ? the upper byte of the 16-bit index register (h:x) in the cpu08. h ? the half-carry bit in the condition code register of the cpu08. this bit indicates a carry from the low-or der four bits of the accumulator value to the high-order four bits . the half-carry bit is required for binary-coded decimal arithmetic operations. the decimal adjust accumulator (daa) instru ction uses the state of the h and c bits to determine the appropriate correction factor. hexadecimal ? base 16 numbering system that uses the digits 0 through 9 and the le tters a through f. high byte ? the most significant eight bits of a word. illegal address ? an address not within the memory map illegal opcode ? a non-existent opcode. non-disclosure agreement required glossary technical data MC68HC708MP16 ? rev. 3.1 388 glossary freescale semiconductor i ? the interrupt mask bit in the condition code r egister of the cpu08. when i is set, all inte rrupts are disabled. index register (h:x) ? a 16-bit register in th e cpu08. the upper byte of h:x is called h. the lower byte is calle d x. in the indexed addressing modes, the cpu uses t he contents of h:x to determine the effective address of the oper and. h:x can also serve as a temporary data storage location. input/output (i/o) ? input/output interfac es between a computer system and the external world. a c pu reads an input to sense the level of an external si gnal and writes to an output to change the level on an external signal. instructions ? operations that a cpu can perform. instructions are expressed by programmers as assembly language mnemonics. a cpu interprets an opcode an d its associated operand(s) and instruction. interrupt ? a temporary break in the sequential exec ution of a program to respond to signals from peripheral devic es by executing a subroutine. interrupt request ? a signal from a peripheral to the cpu intended to cause the cpu to ex ecute a subroutine. i/o ? see input/output (i/0). irq ? see external in terrupt module (irq). jitter ? short-term si gnal instability. latch ? a circuit that retains the voltag e level (logic 1 or logic 0) written to it for as long as power is applied to the circuit. latency ? the time lag between inst ruction completion and data movement. least significant bit (lsb) ? the rightmost digi t of a binary number. logic 1 ? a voltage level approximately equal to the inpu t power voltage (v dd ). glossary MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor glossary 389 non-disclosure agreement required logic 0 ? a voltage level approximatel y equal to t he ground voltage (v ss ). low byte ? the least significant eight bits of a word. low voltage inhibi t module (lvi) ? a module in t he m68hc08 family that monitors power supply voltage. lvi ? see low voltage inhibit module (lvi). m68hc08 ? a freescale fami ly of 8-bit mcus. mark/space ? the logic 1/logic 0 convent ion used in formatting data in serial communication. mask ? 1. a logic circuit that forces a bit or group of bits to a desired state. 2. a photomask used in integr ated circuit fabrication to transfer an image onto silicon. mask option ? an optional micr ocontroller feature that the customer chooses to enabl e or disable. mask option register (mor) ? an eprom location c ontaining bits that enable or disable certain mcu features. mcu ? microcontroller unit. see microcontroller. memory location ? each m68hc08 memory location holds one byte of data and has a unique ad dress. to store info rmation in a memory location, the cpu places the addr ess of the location on the address bus, the data informat ion on the data bus, and asserts the write signal. to read information from a memory location, the cpu places the address of the location on the address bus and asserts the read signal. in response to the read signal, the sele cted memory location places its data onto the data bus. memory map ? a pictorial repres entation of all memo ry locations in a computer system. microcontroller ? microcontroller unit (m cu). a complete computer system, including a cpu, memo ry, a clock oscillator, and input/output (i/o) on a si ngle integrated circuit. non-disclosure agreement required glossary technical data MC68HC708MP16 ? rev. 3.1 390 glossary freescale semiconductor modulo counter ? a counter that can be programmed to count to any number from zero to its maximum possible modulus. monitor rom ? a section of rom that can execute commands from a host computer for testing purposes. mor ? see mask option register (mor). most significant bit (msb) ? the leftmost digi t of a binary number. multiplexer ? a device that can select one of a number of inputs and pass the logic level of that input on to the output. n ? the negative bit in t he condition code regist er of the cpu08. the cpu sets the negative bit when an arithmet ic operation, logical operation, or data manipulati on produces a negative result. nibble ? a set of four bi ts (half of a byte). object code ? the output from an assembler or compiler that is itself executable machine code, or is su itable for processing to produce executable machine code. opcode ? a binary code that instructs the cpu to perform an operation. open-drain ? an output that ha s no pullup transistor. an external pullup device can be connected to the power supply to provide the logic 1 output voltage. operand ? data on which an operation is performed. usually a statement consists of an operator and an operand. for example, the operator may be an add in struction, and the operand may be the quantity to be added. oscillator ? a circuit that produces a c onstant frequency square wave that is used by the computer as a timing and sequencing reference. otprom ? one-time programmable read- only memory. a non-volatile type of memory that cannot be reprogrammed. overflow ? a quantity that is too large to be contai ned in one byte or one word. page zero ? the first 256 bytes of me mory (addresses $0000?$00ff). glossary MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor glossary 391 non-disclosure agreement required parity ? an error-checking scheme that counts the number of logic 1s in each byte transmitted. in a system that uses odd par ity, every byte is expected to have an odd number of logic 1s. in an even parity system, every byte should have an even number of logic 1s. in the transmitter, a parity gener ator appends an extra bi t to each byte to make the number of l ogic 1s odd for odd pa rity or even for even parity. a parity checker in the rece iver counts the number of logic 1s in each byte. the parity checker generat es an error signal if it finds a byte with an incorrec t number of logic 1s. pc ? see program counter (pc). peripheral ? a circuit not under direct cpu control. phase-locked loop (pll) ? an oscillator circui t in which the frequency of the oscillator is synchro nized to a re ference signal. pll ? see phase-locked loop (pll). pointer ? pointer register. an index register is sometimes called a pointer register because its contents are used in the calculation of the address of an operand, and therefore point s to the operand. polarity ? the two opposite logic levels , logic 1 and logic 0, which correspond to two differ ent voltage levels, v dd and v ss . polling ? periodically reading a status bi t to monitor the condition of a peripheral device. port ? a set of wires for communi cating with off-chip devices. prescaler ? a circuit that generates an out put signal related to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10, etc. program ? a set of computer instructions that ca uses a computer to perform a desired operat ion or operations. program counter (pc) ? a 16-bit register in the cpu08. the pc register holds the addre ss of the next instruct ion or operand that the cpu will use. pull ? an instruction that copies into the accumulator the contents of a stack ram location. the stack ram address is in the stack pointer. non-disclosure agreement required glossary technical data MC68HC708MP16 ? rev. 3.1 392 glossary freescale semiconductor pullup ? a transistor in t he output of a logic ga te that connects the output to the logic 1 volt age of the power supply. pulse-width ? the amount of time a signal is on as opposed to being in its off state. pulse-width modulation (pwm) ? controlled variati on (modulation) of the pulse width of a signa l with a constant frequency. push ? an instruction that copies the contents of the accumulator to the stack ram. the stack ram addre ss is in the stack pointer. pwm period ? the time requir ed for one complete cycle of a pwm waveform. ram ? random access memory. all ra m locations ca n be read or written by the cpu. the contents of a ram memory location remain valid until the cpu writes a different value or until power is turned off. rc circuit ? a circuit consisting of c apacitors and resistors having a defined time constant. read ? to copy the contents of a memo ry location to the accumulator. register ? a circuit that st ores a group of bits. reserved memory location ? a memory location that is used only in special factory-test modes. writ ing to a reserved location has no effect. reading a reserved locati on returns an unpredictable value. reset ? to force a device to a known condition. rom ? read-only memory. a type of memory that can be read but cannot be changed (written). the co ntents of rom must be specified before manufacturing the mcu. sci ? see serial communicati on interface module (sci). serial ? pertaining to sequential tr ansmission over a single line. serial communica tion interface module (sci) ? a module in the m68hc08 family that supports asynchronous communication. serial peripheral inte rface module (spi) ? a module in the m68hc08 family that supports synchronous communicaton. glossary MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor glossary 393 non-disclosure agreement required set ? to change a bit from logic 0 to logic 1; opposi te of clear. shift register ? a chain of circuits that can retain the logic levels (logic 1 or logic 0) written to them and that can shift the logic levels to the right or left thr ough adjacent circui ts in the chain. signed ? a binary number not ation that accommodates both positive and negative numbers. the most significant bit is used to indicate whether the number is positive or negative, normal ly logic 0 for positive and logic 1 for negative. the other seven bits indicate the magnitude of the number. sim ? see system inte gration module (sim). software ? instructions and data that control the operation of a microcontroller. software interrupt (swi) ? an instruction that causes an interrupt and its associated vector fetch. spi ? see serial peripheral interface module (spi). stack ? a portion of ram reserved for st orage of cpu regi ster contents and subroutine return addresses. stack pointer (sp) ? a 16-bit register in the cpu08 containing the address of the next available storage location on the stack. start bit ? a bit that signals the beginni ng of an asynchronous serial transmission. status bit ? a register bit t hat indicates the c ondition of a device. stop bit ? a bit that signals the e nd of an asynchronous serial transmission. subroutine ? a sequence of instructions to be used more than once in the course of a progra m. the last instruction in a subroutine is a return from subroutine (rts) instru ction. at each pl ace in the main program where the subroutine ins tructions are needed, a jump or branch to subroutine (jsr or bsr) instruction is us ed to call the subroutine. the cpu leav es the flow of the ma in program to execute the instructions in the subroutin e. when the rts instruction is executed, the cpu return s to the main program where it left off. non-disclosure agreement required glossary technical data MC68HC708MP16 ? rev. 3.1 394 glossary freescale semiconductor synchronous ? refers to logic circui ts and operations that are synchronized by a co mmon reference signal. system integration module (sim) ? one of a number of modules that handle a variety of contro l functions in the mo dular m68hc08 family. the sim controls mode of operation, resets and interrupts, and system clock distribution. tim ? see timer interface module (tim). timer interface module (tim) ? a module used to relate events in a system to a point in time. timer ? a module used to relate events in a system to a point in time. toggle ? to change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0. tracking mode ? mode of low-jitter pll operation during which the pll is locked on a frequency. also see acquisition mode. two?s complement ? a means of performing binary subtraction using addition techniques. the most signific ant bit of a two?s complement number indicates the si gn of the number (1 indicates negative). the two?s complement negative of a numbe r is obtained by inverting each bit in the number and t hen adding 1 to the result. unbuffered ? utilizes only one register fo r data; new data overwrites current data. unimplemented memory location ? a memory location that is not used. writing to an uni mplemented location has no effect. reading an unimplemented location re turns an unpredictable value. executing an opcode at an unimplem ented location caus es an illegal address reset. v ?the overflow bit in t he condition code regist er of the cpu08. the cpu08 sets the v bit w hen a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow bit. variable ? a value that changes duri ng the course of program execution. glossary MC68HC708MP16 ? rev. 3.1 technical data freescale semiconductor glossary 395 non-disclosure agreement required vco ? see voltage-cont rolled oscillator. vector ? a memory location that cont ains the address of the beginning of a subroutine written to se rvice an interrupt or reset. voltage-controlled oscillator (vco) ? a circuit that produces an oscillating output signal of a frequ ency that is controlled by a dc voltage applied to a control input. waveform ? a graphical representation in which the amplitude of a wave is plotted against time. wired-or ? connection of circui t outputs so that if any output is high, the connection point is high. word ? a set of two bytes (16 bits). write ? the transfer of a byte of data from the cpu to a memory location. x ? the lower byte of the index register (h:x) in the cpu08. z ? the zero bit in the condition code register of the cpu08. the cpu08 sets the zero bit when an arithmetic operation, logical operation, or data manipulati on produces a result of $00. non-disclosure agreement required glossary technical data MC68HC708MP16 ? rev. 3.1 396 glossary freescale semiconductor how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the arm powered logo is a registered trademark of arm limited. arm7tdmi-s is a trademark of arm limited. java and all other java-based marks are trademarks or registered trademarks of sun microsystems, inc. in the u.s. and other countries. the bluetooth trademarks are owned by their proprietor and used by freescale semiconductor, inc. under license. ? freescale semiconductor, inc. 2005. all rights reserved. rev. 3.1 MC68HC708MP16/d july 28, 2005 |
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